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Autor Tema: Estructuras Binarias x86-64  (Leído 768 veces)
FFernandez

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Estructuras Binarias x86-64
« en: 6 Junio 2020, 21:47 »

Primera parte:  
Este es un manual indirecto de las estructuras binarias del juego de instrucciones x86-64, está abierto a edición constructiva.
Este prefijo es opcional puede estar presente o no, se enumeran los casos en los que puede estar presente. De momento se representa la forma Hexadecimal del mismo.




// LEGANCY PREFIX

/*
0x66 h     ANULACION DEL TAMAÑO PREDETERMINADO DE OPERANDOS Operand-Size Override   IN 64   PREDETeRMINADO 32----------EFECTIVE 16

0x67h  Address-Size Overrides   IN 64  -----EFECTIVE 32

Ojo  In 64-bit mode, the CS, DS, ES, and SS segment overrides are ignored
0x2Eh  Forces use of current CS segment for memory operands.
0x3Eh Forces use of current DS segment for memory operands.
0x26h Forces use of current ES segment for memory operands.
0x64h Forces use of current FS segment for memory operands.
0x65h Forces use of current GS segment for memory operands.
0x36h Forces use of current SS segment for memory operands.
*/
/*
El prefijo LOCK solo se puede usar con las formas de las siguientes instrucciones que escriben una memoria y: ADC, ADD, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XADD, XCHG y XOR. Se produce una excepción de código de operación no válido si el prefijo LOCK se usa con cualquier otra instrucción.
0xF0h LOCK        El byte de prefijo de repetición / bloqueo garantiza que la instrucción tendrá uso exclusivo de toda la memoria compartida, hasta que la instrucción complete la ejecución:


BT, BTS, BTR, BTC                   mem, reg/imm
XCHG                                reg, mem
XCHG                                mem, reg
ADD, OR, ADC, SBB, AND, SUB, XOR    mem, reg/imm
NOT, NEG, INC, DEC                  mem


Prefijos de repetición

Instrucciones que no pueden usar prefijos de repetición. En general, los prefijos de repetición solo se deben usar en las instrucciones de cadena enumeradas en las tablas 1-6, 1-7 y 1-8 . Para otras instrucciones (principalmente instrucciones SIMD), los prefijos 66h, F2h y F3h se usan como modificadores de instrucciones para extender el espacio de codificación de instrucciones en los mapas de código de operación 0Fh, 0F_38h y 0F_3Ah




1-6

REP Prefix Opcodes  (0xF3h) también se usa como prefijo obligatorio para la instrucción POPCNT, LZCNT y ADOX.
Ejemplo: ADOX reg64, reg/mem64              F3 0F 38 F6 /r       Añadir sin firmar con indicador de desbordamiento

        



REP INS reg/mem8, DXREP INSB  F3 6C  
REP INS reg/mem16/32, DXREP INSWREP INSD F3 6D
REP LODS mem8 REP LODSB F3 AC
REP LODS mem16/32/64 REP LODSWREP LODSDREP LODSQ F3 AD
REP MOVS mem8, mem8REP MOVSB F3 A4
REP MOVS mem16/32/64, mem16/32/64 REP MOVSWREP MOVSDREP MOVSQ F3 A5
REP OUTS DX, reg/mem8 REP OUTSB F3 6E
REP OUTS DX, reg/mem16/32 REP OUTSWREP OUTSD F3 6F
REP STOS mem8REP STOSB F3 AA
REP STOS mem16/32/64 REP STOSWREP STOSDREP STOSQ  F3 AB

1-7

REPE and REPZ Prefix Opcodes  ( 0xF3h)
REPx CMPS mem8, mem8REPx CMPSB F3 A6
REPx CMPS mem16/32/64, mem16/32/64 REPx CMPSWREPx CMPSDREPx CMPSQ F3 A7
REPx SCAS mem8 REPx SCASB F3 AE
REPx SCAS mem16/32/64 REPx SCASWREPx SCASDREPx SCASQ F3 AF

1-8
REPNE and REPNZ Prefix Opcodes  (F2)
REPNx CMPS mem8, mem8REPNx CMPSB F2 A6
REPNx CMPS mem16/32/64, mem16/32/64 REPNx CMPSWREPNx CMPSDREPNx CMPSQ F2 A7
REPNx SCAS mem8REPNx SCASBF2 AEREPNx SCAS mem16/32/64 REPNx SCASWREPNx SCASDREPNx SCASQ F2 AF



*/

Segunda Parte


/*
// REX PREFIX
   0X40h a 0X4Fh

¡Este Prefijo no simpre esta presente!

      FORMATO  del Byte REX (0100 WRXB)

Hay que tener en cuenta que hablaremos de un procesador y sistema operativo de 64 bits.

En un sistema de 64 bits el operando predeterminado es de 32 bits.

Si W = 0  implica que no se cambia el tamaño del operando.
Si W= 1   implica que se cambia el tamaño del operando a 64 bits.

R es una extensión del REG del (Byte M0Dr/m)(*)
X es una extensión del Índice del (SIB Byte) ¿si existe? Sino es ignorado (*)
B es una extensión de la BASE del (SIB Byte) ¿si existe? En caso
Contrario es una extensión del r/m del (Byte M0Dr/m)(*)

RexPrefix (40,41,42,43,44,45,46,47,48,49,4A,4B,4C,4D,4E,4F)
Notación      Rex.w = 1        (48 49 4A 4B 4C 4D 4E 4F)  64 bits

    
    
Byte MOD r/m      (MOD 2 bits, REG 3 bits, r/m 3 bits)
SIB Byte                  (Escala 2 bits, Índice 3 bits, Base 3 bits)


Byte MOD r/m




MOD
(00)   direccionamiento indirecto  ojo. No hay desplazamiento
(01)   1 byte de desplazamiento
(10) 4 byte de desplazamiento
(11) direccionamiento directo a registro  ojo. No hay desplazamiento solo Imm...

En estos casos : { "C0", "C8", "D0", "D8", "E0", "EB", "F0", "F8", "C1", "C9", "D1", "D9", "E1", "E9", "F1", "F9", "C2", "CA", "D2", "DA", "E2", "EA", "F2", "FA", "C3", "CB", "D3", "DB", "E3", "EB", "F3", "FB", "C4", "CC", "D4", "DC", "E4", "EC", "F4", "FC", "C5", "CD", "D5", "DD", "E5", "ED", "F5", "FD", "C6", "CE", "D6", "DE", "E6", "EE", "F6", "FE", "C7", "CF", "D7", "DF", "E7", "EF", "F7", "FF" }


REG
de datos(000, 001,010,011)
Punteros de pila(100,101)
Registros de índices(110,111)

r/m                            Direccionamiento efectivo
de datos(000, 001,010,011)  + desplazamiento
(100) indica que existe el    SIB Byte  

SIB Presente { "04", "0C", "14", "1C", "24", "2C", "34", "3C", "44", "4C", "54", "5C", "64", "6C", "74", "7C", "84", "8C", "94", "9C", "A4", "AC", "B4", "BC" }


Si (101) solo hay desplazamiento
En estos casos: { "05", "00", "15", "1D", "25", "2D", "35", "3D" }  mod (00)  Ojo 32 Bits


 Registros de índices(110,111) + desplazamiento



  SIB Byte


Escala    (Índice * Escala)Valué          
(00)   =  1
(01)   = 2
(10)            = 4
(11)            = 8


Indece

de datos(000, 001,010,011)
Registros de índices(110,111)
Punteros de pila(101)
(100)      no hacer nada

BASE
de datos(000, 001,010,011)
Registros de índices(110,111)
Punteros de pila(100)
(101)    Solamente desplazamiento si MOD = (00), si MOD =(01) OR (10) Punteros de pila
MOD (11) no utilizado

Direccionamiento efectivo con el SIB Byte
[Índice * Escala]  + desplazamiento(viene predeterminado por MOD del Byte MOD r/m)




¡Ojo!

El direccionamiento de desplazamiento en modo de 64 bits utiliza codificaciones ModR / M y SIB existentes de 32 bits. Los tamaños de desplazamiento ModR / M y SIB no cambian. Permanecen 8 bits o 32 bits y se extienden a 64 bits.


Registros de segmento Predeterminados

El registro de segmento predeterminado es SS para las direcciones efectivas que contienen un índice BP, DS para otras direcciones efectivas

Si    r/m = (010) or (011)   el registro de segmento predeterminado es SS
Si     r/m =(000) or (001) or (100) or (101) or (110) or (111) el registro de segmento predeterminado es  DS

Ejemplo de Mnemonic  ADD  ( Z000 0XDS )

S=0 8bits Operando           S=1 16-32Bits Operando
D=1 Indica que el operando(destino) es el REG del MODr/m
D=0 Indica que el operando(destino) es el indicado por MOD......r/m del MODr/m
¿Si Z=1 y D=0 indica que el tamaño del imm..  esta establecido por S
¿Si Z=1 y D=1 indica que el tamaño de imm.. se extenderá al tamaño del operando
¿Si X=1  indica que el operando es un registro predeterminado Al, AX, EAX RAX segun el tamaño expresado por "S" con sus Prefijos correspondientes si es diferente a 8 o 32 Bits.

Hay que tener en cuenta que el operando predeterminado es de 32 bits
y el Direccionamiento se extiende a 64 bits en sistemas de 64.
imm…  Inmediato Valué
r… Registros generales     AL-8   AX- 16    EAX- 32  RAX- 64 bits    hay 8 en total (AL CL DL BL AH CH DH BH)  
(Inmediato)imm8 = 8 bits         imm16= 16 bits  imm32 = 32 bits etc.….



0x00h     0000 0000      [MOD=(11)  REG=(000)    r/m(000)]= 0x00h           ADD r/m, r8  *                00 (00) r.. variable

Longitud de esta instrucion     1 Byte del OpCode + 1 Byte del MODr/m  Total 2 Bytes

El destino de la operacion es el MODr/m porque lo indica el digito "D"=0
por lo tanto el origen es el REG


MOD =(11) indica que la operacion es de registro a registro.

0x01h     0000 0001        [MOD=(11)  REG=(000)    r/m(000)]= 0xC0h           ADD r/m, r16   *       66  01 (C0) r.. variable
0x02 h     0000 0010        [MOD=(11)  REG=(000)     r/m(000)]= 0xCOh           ADD r8, r/m  *               02  (C0) r .. variable  
0x03h      0000 0011       [MOD=(11)  REG=(000)    r/m(000)]= 0xCOh           ADD r16, r/m   *             66 03 C0  

X=1 Indica que el Operando(Destino) es el registro de uso general predeterminado (AL,AX,EAX,RAX,XMM0)

0x04h      0000 0100     (04) (imm8)         ADD AL, imm8                       modo directo    ok
0x05h     0000 0101           66 05   (imm16)    ADD AX, imm16           modo directo    ok
0x05h      0000 0101     05 (imm32)        ADD EAX, imm32                    modo directo     ok

En el caso Z = 1 el REG del Byte MODr/m (000) es una extensión del OpCODE Z.
El Operando(destino) es siempre el MOD......r/m.


0x80h      1000 0000         [MOD=(00)  REG=(000)   r/m(000)]= 0x00h           ADD r/m, imm8   *
0x81h      1000 0001        [MOD=(00)  REG=(000)     r/m(000)]          ADD r/m, imm16    *      66  81 (80) r..variable
0x81h      1000 0001         [MOD=(00)  REG=(000)    r/m(000)]          ADD r/m, imm32   *
0x83h      1000 0011      [MOD=(00)  REG=(000)     r/m(000)]           ADD r/m, imm8    *   se extiende imm8 a 32bits        


Esto se aplica a todas estas instrucciones aritméticas-lógicas

REG (000) ADD
REG  (001)  OR
REG  (010) ADC
REG  (011) SBB
REG  (100) AND
REG  (101) SUB
REG  (110) XOR
REG  (111) CMP





El byte SIB


Normalmente no está presente. Solo es necesario cuando una instrucción usa el formato de direccionamiento ( Scale * Index + Base). esto solamente lo indica en Byte MODr/m  si el Campo Registro = (100)=REG.
(Escala 2 BITS, Índice 3 bits, Base 3 Bits)


un ejemplo rápido

ADD ecx, [ebx + edi x 4]    = 0x030CBBh
ADD                        MODr/m            SIB
0 0000 0 1 1       00 001 100       10 111 011


Una parte importante es el desplazamiento, mejor un ejemplo:


ADD ebp,[disp32 + eax*1] = 0x03, 0x2C, 0x05, 0x00, 0x00, 0x00, 0x00
        ADD            modR/M           SIB Byte                            Disp32
= 00000011     00 101 100      00 000 101       00000000 00000000 00000000


ADD ebp,[0x11 + eax*1] = 0x03, 0x2C, 0x05,     0x11, 0x00, 0x00, 0x00 Total Bytes 3+4=7

                                                                               Disp32(0x11h)  se desplaza a la izquierda
= 00000011 00 101 100 00 000 101        00010001 00000000 00000000


ADD ebp,[0x11 + 0x11*4] = 0x03, 0x2C, 0x25, 0x55, 0x00, 0x00, 0x00


IMPORTANTICIMO NUNCA PERDER DE VISTA EL MODO DEL SISTEMA OPERATIVO 32 O 64
El ejemplo anterior corre en un sistema de 32 bits. ¿qué ocurre si corre en un sistema de 64 Bits?

     Recordatorio             0x67h  Address-Size Overrides   IN 64  -----EFECTIVE 32  
      
ADD ebp,[0x11 + eax*1] = 0x67, 0x03, 0x2C, 0x05,  0x11, 0x00, 0x00, 0x00 Total Bytes 1+3+4=8

             L-Prefix                ADD           modR/M           SIB Byte                            Disp32

=        01100111        00000011    00 101 100       00 000 101        00010001 00000000 00000000
                                        
Hemos utilizado el EAX 32 bits, si hubieramos utilizado RAX de 64 bis no haria falta el prefijo.



Algunos Valúes  Aritméticos - Lógicos


ADD x,y       xValue= (x+y)

ADC x,y       xValue= (x+y+CF)

SUB x,y       xValue= (x-y)

SBB x,y       xValue= (x-y-CF)

INC x         xValue= (x+1)

DEC x         xValue= (x-1)

NOT x=(0001)  xValue= (1110)  invierte los bits

NEG x=(1110)  xValue= [(0001)+1]= (0010) invierte los bits y le suma 1

OR x,y  x=(1110) y=(0011)   xValue=(1101)  if (bitx=bity) = 0  else = 1

AND x,y x=(1110) y=(0011)   xValue=(0010) if (bitx=1 y bity=1)=1 else =0

CMP x,y   if x=y Then (ZF (zero flag) gets a value=1) else =0

JMP x         Goto x


// VEX y XOP PREFIX

2 Bytes opecode
0xC5h   VEX

11000100     W vvvv L pp    W=0 fijo
map_select  00001         fijo
Implícito X=1 B=1


3 Bytes opecode
0xC4h VEX

11000101     RXB mmmmm       W vvvv L PP

0X8Fh    XOP
10001111     RXB mmmmm      W vvvv L PP


R
R = 1  obligatorio en 32 bits =  rex.r=0
R = 0  64 bits  = rex.r=1
R es una extensión del REG del (Byte M0Dr/m)(*)

X
X = 1   obligatorio en 32 bits
X=0     64 bits    
X es una extensión del Índice del (SIB Byte) ¿si existe? Sino es ignorado (*)

B
B = 1    ignorado en 32 bits                
B=0        64 bits  
B es una extensión de la BASE del (SIB Byte) ¿si existe? En caso
Contrario es una extensión del r/m del (Byte M0Dr/m)(*)


código de operación específico (uso como REX.W, o usado para código de operación
extensión, o ignorado, dependiendo del byte del código de operación)

W         =   REX.W INVERSO
Si W = 1  implica que no se cambia el tamaño del operando.
Si W= 0   implica que se cambia el tamaño del operando a 64 bits.



mmmmm       Mapa Selecionado
VEX
00000  reservado
00001  byte de código de operación inicial 0F implícito          opcode   Mapa 1   2 Byte
00010                                                                   0F 38       opcode  Mapa 2   3 Byte
00011                                                                   0F 3A       opcode  Mapa 3   3 Byte
00100  reservado
11111  reservado

XOP
00000 – 00111  Reservdo
01000 XOP opcode map 8
01001 XOP opcode map 9
01010 XOP opcode map 10
(Ah)01011 – 11111Reserved

vvvv
Es un especificador de registro (en forma de complemento de 1)
o 1111 si no se usa?¿
vvvv
Binary    Register           Binary              Register
0000    XMM15/YMM15      1000          XMM07/YMM07
0001    XMM14/YMM14      1001          XMM06/YMM06
0010    XMM13/YMM13      1010           XMM05/YMM05
0011    XMM12/YMM12      1011           XMM04/YMM04
0100    XMM11/YMM11      1100            XMM03/YMM03
0101     XMM10/YMM10     1101            XMM02/YMM02
0110     XMM09/YMM09     1110            XMM01/YMM01
0111     XMM08/YMM08     1111            XMM00/YMM00



L =0       scalar o 128 bits vector  
L= 1      256 Bits Vector

En Instruciones de Mascara

L=0  2 operandos in mascara
L=1  3 operandos in mascara


PP
Extensión de código de operación que proporciona la funcionalidad equivalente de un prefijo SIMD

00 None
01  66
10  F3
11  F2


VEX Byte 1, el bit [7] contiene un bit análogo a un REX.R invertido. En los modos protegido y de compatibilidad, el bit debe establecerse en "1"; de lo contrario,
la instrucción es LES o LDS.
El bit [6] del byte VEX de 3 bytes codifica un bit análogo a un bit REX.X invertido. Es una extensión del campo Índice SIB en modos de 64 bits. En los modos de 32 bits, este bit debe establecerse en "1"; de lo contrario, la instrucción es LES o LDS. Este bit solo está disponible en el prefijo VEX de 3 bytes. Este bit se
almacena en formato invertido.
El bit [5] del byte VEX de 3 bytes codifica un bit análogo a un REX.B invertido. En los modos de 64 bits, es una extensión del campo ModR / M r / m, o el campo base SIB.
En los modos de 32 bits, este bit se ignora. Este bit solo está disponible en el prefijo VEX de 3 bytes. Este bit se almacena en formato de bit invertido
El bit [7] del byte 2 VEX de 3 bytes está representado por la notación VEX.W. Puede proporcionar las siguientes funciones, dependiendo del código de operación específico.

• Para las instrucciones AVX que tienen instrucciones SSE heredadas equivalentes (por lo general, estas instrucciones SSE tienen un operando de registro de propósito general con su atributo de tamaño de operando promocionable por REX.W), si REX.W promueve el atributo de tamaño de operando del operando de registro de propósito general en la instrucción SSE heredada, VEX.W tiene el mismo significado en la forma equivalente AVX correspondiente. En los modos de 32 bits, VEX.W se ignora en silencio.

• Para las instrucciones AVX que tienen instrucciones SSE heredadas equivalentes (por lo general, estas instrucciones SSE tienen oper-ands con su atributo de tamaño de operando fijo y no promocionable por REX.W), si REX. A W no le importa la instrucción SSE heredada, VEX.W se ignora en la forma equivalente de AVX correspondiente independientemente del modo.

• Para las nuevas instrucciones AVX donde VEX.W no tiene una función definida (por lo general, esto significa la combinación del byte de código de operación y VEX.mmmmm no tenía ninguna función SSE equivalente), VEX.W está reservado como cero y si se configura en un valor distinto de cero, la instrucción será #UD

2 bytes VEX Byte 1, bits [6: 3] y 3 bytes VEX Byte 2, bits [6: 3] - 'vvvv' el Especificador de registro de origen o destino En modo de 32 bits, el primer byte VEX C4 y C5 alias las instrucciones LES y LDS.

Para mantener la compatibilidad con los programas existentes, el segundo byte VEX, los bits [7: 6] deben ser 11b. Para lograr esto, los bits de carga útil VEX se seleccionan para colocar solo campos válidos invertidos de 64 bits (selectores de registro extendido) en estos bits superiores.

El VEX de 2 bytes Byte 1, bits [6: 3] y el VEX de 3 bytes, Byte 2, bits [6: 3] codifican un campo (abreviatura VEX.vvvv) que para instrucciones con 2 o más registros fuente y un XMM o YMM o destino de memoria codifica el primer especificador de registro fuente almacenado en forma invertida (complemento de 1). VEX.vvvv no es utilizado por las instrucciones con una fuente (excepto ciertos turnos, ver más abajo) o en instrucciones sin XMM o YMM o destino de memoria.

Si una instrucción no usa VEX.vvvv, entonces debe establecerse en 1111b; de lo contrario, la instrucción será # UD.
En el modo de 64 bits, se pueden usar los 4 bits. el bit 6 debe ser 1 (si el bit 6 no es 1, la versión VEX de 2 bytes generará instrucción LDS y la versión VEX de 3 bytes ignorará este bit

El campo VEX.vvvv está codificado en formato de bit invertido para acceder a un operando de registro
*/

Continuare pronto.........................

3DNow!™
      Formato y        Opcodes
0x0F0Fh

0Fh 0Fh [ModRM] [SIB] [displacement] imm8_opcode

[/b][/size]

EVEX PREFIX
  
0X62h
R X B r  00 mm
W vvvv 1 pp
z l L b V aaa

PREFIX      62        1º   2º    3º  

mm             selección mapa

PP
Extensión de código de operación que proporciona la funcionalidad equivalente de un prefijo SIMD

00 None
01  66
10  F3
11  F2

RXB         Extensión del M/m, M/r , SIB/b y SIB/índice

r     Extensión del  EVEX.R and ModR/M.reg

X  Extensión del  EVEX.B and ModR/M.rm, SIB/VSIB si esta presente

vvvv
Es un especificador de registro (en forma de complemento de 1)
o 1111 si no se usa?¿

V  Extensión del  EVEX.vvvv , VSIB si esta presente Especificador de registro NDS / VIDX High-16


aaa Especificación de registro de máscara de operaciones integrada
Las instrucciones que requieren aaa <> 000 no permiten que EVEX.z se establezca en 1.

W   extensión de tamaño

Z     enmascaramiento (fusión y puesta a cero)

b            Broadcast/RC/SAE Context
b=1
Instrucciones de FP con redondeo semántico.
Instrucciones de carga + operación con fuente de memoria
b= 0
Para :Otras instrucciones (carga / almacenamiento / difusión / recopilación / dispersión explícitas)


l                Vector length/RC
l L        
00b: 128-bit  01b: 256-bit  10b: 512-bit    11b: Reservado (#UD)





Instrucciones que requieren el vector:       XCR0 Bit Vector [7:0]

Legacy SIMD prefix Instrucciones codificadas (e.g SSE)XMM
xxxxxx11b

VEX- Instrucciones codificadas operando en YMM YMM
xxxxx111b

EVEX-codificadas 128-bit Instrucciones ZMM
111xx111b

EVEX- codificadas 256-bit Instrucciones ZMM
111xx111b

EVEX-encoded 512-bit Instrucciones ZMM
111xx111b

VEX- codificadas  Instrucciones operando en  opmaskk-reg
xx1xxx11b


vmulps zmm1, zmm2, [rax] {1to16}

0x62, 0xF1, 0x6C, 0x58, 0x59, 0x08


    0º         1º         2º         3º    
{ 0x62,    0xF1,    0x6C,   0x58,    0x59,        0x18 }

  pref                                         op/s mapa    r/m


 Broadcast  (escalar) r/m


                        
                     zlLbVaaa

58 (1 to 16)    01011000  operando en zmm con reg de 64 bits

18  (1 to 4)    00011000  operando en xmm con reg de 32 bits


AVX-512 Opmask registers


Ejemplo de codificacion completo
 

Opcode Operando destino, operando, operando field

KANDW k1, k2, k3     modificamos el Operando destino k1

Prefixo VEX  +  W vvvv L pp + Opcode   + M/r
  
c5 ec 41 cb    k1   k2   k3           W vvvv L pp              M/r   11 001 011    k1 = base = 1

KANDW k4, k2, k3
c5 ec 41 e3    k4   k2   k3                                   M/r    11 100  011   k4 = base = 4

KANDW k7, k2, k3
c5 ec 41 fb    k7   k2   k3           1 1101 1 00                     11 111 011   k7 = base = 7



KANDW k1, k2, k3


c5 ec 41 cb    k1   k2   k3           W vvvv L pp              M/r   11 001 011     k3= m/r =3  

KANDW k1, k2, k4

c5 ec 41 cc                                                          11 001 100      k4= m/r =4

KANDW k1, k2, k7                                                      

c5 ec 41 cf                                                          11 001 111      k7= m/r =7    



KANDW k1, k2, k3                      

c5 ec 41 cb                            1 1101 1 00            101 bits invertidos 010 = 2 =k2

KANDW k1, k4, k3

c5 dc 41 cb                            1 1011 1 00            011 bits invertidos 100 = 4 =k4


KANDW k1, k7, k3

c5 c4 41 cb                             1 1000 1 00           000 bits invertidos 111 = 7 =k7

 
Aqui se codifica el Operando que en este caso no tiene sentido, pero se trata igual.

El Opcode lleva implicito que es una operacion con mascara "Opmask"


                                        




Static Rounding Mode  (EVEX.b = 1)   SAE CONTROL     aqui el Ll indica el round         

vaddps zmm7 {k6}, zmm2, zmm4, {rd-sae}

0x62, 0xF1, 0x6C, 0x3E, 0x58, 0xFC



                      zlLbVaaa
3E   rd-sae     00111110

5e   ru-sae     01011110

1E   rn-sae     00011110

7E   rz-sae     01111110

« Última modificación: 25 Junio 2020, 00:20 por FFernandez » En línea

FFernandez

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Mensajes: 44


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Re: Estructuras Binarias x86-64
« Respuesta #1 en: 16 Julio 2020, 21:02 »

CREANDO DESENSAMBLADOR


PRIMERO LA BASE DE DATOS GENERICA



ESTA SE APLICA A INTEL Y AMD, YA VEREMOS LAS DIFERENCIAS DE MOMENTO CONVERGEN


// UN OPCODE******************************************************************************************************************************************************************************

         string[] UnOpcodeMasMRm = new string[] { "00", "01", "02", "03", "06", "07", "10", "11", "12", "13", "16", "17", "20", "21", "22", "23", "30", "31", "32",
            "33", "63", "84", "85", "86", "87", "08", "09", "0A", "0B", "18", "19", "1A", "1B", "28", "29", "2A", "2B", "38", "39", "3A", "3B", "88", "89", "8A", "8B", "8C", "8D", "8E" };
        string[] UnOpcodeMasImm8 = new string[] { "04", "14", "24", "34", "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", "D4", "D5", "E4", "E5", "E6", "E7", "0C", "1C", "2C", "3C", "6A", "A8", "CD", "EB" };
        string[] UnOpcodeMasImm_ = new string[] { "05", "15", "25", "35", "0D", "1D", "2D", "3D", "68", "A9", "B8", "B9", "BA", "BB", "BC", "BD", "BE", "BF" };
        string[] UnOpcodeMasMRMasImm16 = new string[] { "C2" };

        string[] UnOpcodeMasImm16mASImm8 = new string[] { "C8" }; // IMM8(IMM8,00,01)
        string[] UnOpcodeMasImm16 = new string[] { "CA" };

        string[] UnOpcodeMasEspecial = new string[] { "C4", "C5", "62" };  // masMR o vex vex  evex  * LES LDS  BOUND    Ojo hay que saber distinguir  32-64 BITS

        string[] UnOpcodeRex = new string[] { "40", "41", "42", "43", "44", "45", "46", "47", "48", "49", "4A", "4B", "4C", "4D", "4E", "4F" }; //   32-64 BITS    INC  i64 general register / REXo64 Prefixe,  DEC i64 general register / R   eAX  eCX  eDX  eBX eSP eBP eSI  eDI      Ojo hay que saber distinguir


        string[] UnOpcodeSolo = new string[] { "27", "37", "50", "51", "52", "53", "54", "55", "56", "57", "60", "61", "70", "71", "90", "91", "92", "93", "94", "95",
            "96", "97", "A4", "A5", "A6", "A7", "C3", "D7", "F4", "F5", "0E", "1E", "1F", "2F", "3F", "58", "59", "5A", "5B", "5C", "5D", "5E", "5F", "6C", "6D", "6E",
            "6F", "98", "99", "9A", "9B", "9C", "9D", "9E", "9F", "AA", "AB", "AC", "AD", "AE", "AF", "C9", "CB", "CC", "CE", "CF", "EC", "ED", "EE", "EF", "F8", "F9", "FA", "FB", "FC", "FD" };

        string[] UnOpcodeMasDespla8 = new string[] { "70", "71", "72", "73", "74", "75", "76", "77", "A0", "A2", "EO", "E1", "E2", "E3", "78", "79", "7A", "7B", "7C", "7D", "7E", "7F" };
        string[] UnOpcodeMasDespla_ = new string[] { "A1", "A3", "E8", "E9", "EA" };

        string[] UnOpcodeMasMRMasImm8 = new string[] { "69", "6B" };

      

      

        // DOS OPCODES*********************************************************************************************************************************************************************************

        // COMPROBAR REX  DEC   ETC

        // f2 f3 66 67 ojo  MIRAR SHRD OF AD   OJO



        string[] OFDosOpcodeMasMRm = new string[] { "02", "03", "20", "21", "22", "23", "40", "41", "42", "43", "44", "45", "46", "47", "50", "51", "52",
            "53", "54", "55", "56", "57", "60", "61", "58", "59", "5A", "5B", "5C", "5D", "5E", "5F", "68", "69", "6A", "6B", "6C", "6D", "6E", "6F", "78",
            "79", "7C", "7D", "7E", "7F", "90", "91", "92", "93", "94", "95", "A5", "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", "C0", "C1", "C3", "D0",
            "D1", "D2", "D3", "D4", "D5", "D6", "D7", "E0", "E1", "E2", "E3", "E4", "E5", "E6", "E7", "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "98",
            "99", "9A", "9B", "9C", "9D", "9E", "9F", "AB", "AD", "AF", "B8", "BB", "BC", "BD", "BE", "BF", "D8", "D9", "DA", "DB", "DC", "DD", "DE", "DF",
            "E8", "E9", "EA", "EB", "EC", "ED", "EE", "EF", "F8", "F9", "FA", "FB", "FC", "FD", "FE" };


        string[] OFDosOpcodeMasDespla32 = new string[] { "80", "81", "82", "83", "84", "85", "86", "87", "88", "89", "8A", "8B", "8C", "8D", "8E", "8F" };

        string[] A66OFDosOpcodeMasDespla16 = new string[] { "80", "81", "82", "83", "84", "85", "86", "87", "88", "89", "8A", "8B", "8C", "8D", "8E", "8F" };


        string[] OFDosOpcodeSolo = new string[] { "05", "06", "07", "30", "31", "32", "33", "34", "35", "36", "08", "09", "A0", "A1", "A2", "A8", "A9", "AA", "C8", "C9", "CA", "CB", "CC", "CD", "CE", "CF" };



      

        string[] OFDosOpcodeEscapeA4 = new string[] { "38" };
        string[] OFDosOpcodeEscapeA5 = new string[] { "3A" };

      

        // TRES OPCODES********************************************************************************************************************************************************************************

        // pblendvb            vfnmadd132ss/d
        // TRES BYTES  0F38-------------------------------escape 38------------------------------------------------------------


        string[] OF38OpcodeMasMRm = new string[] {"00","01","02","03","04","05","06","07","10","14","15","16","17","20","21","22","23","24,","25","30","31","32","33","34",
              "35","36","37","40","41","45","46","47","80","81","82","90","91","92","93","96","97","A6","A7","B6","B7","F0","F1","F2","F5","F6","F7","08","09","0A","0B","0C","0D","0E","OF",
              "1C","1D","1E","18","19","1A","28","29","2A","2B","2C","2D","2E","2F","38","39","3A","3B","3C","3D","3E","3F","58","59","5A","78","79","8C","8E","98","99","9A",
              "9B","9C","9D","9E","9F","A8","A9","AA","AB","AC","AD","AE","AF","B8","B9","BA","BB","BC","BD","BE","BF","C8","C9","CA","CB","CC","CD","DB","DC","DD","DE","DF"};



        string[] OF38OpcodeMasMRMasImm8 = new string[] { "13" };

        string[] OF38Grupo17_3 = new string[] { "F3" };

        // TRES BYTES  0F3A--------------------------------------escape 3A----------------------------------------------------------

        string[] OF3AOpcodeMasMasMRm = new string[] { "4A", "4B", "4C" };

        string[] OF3AOpcodeMasMRMasImm8 = new string[] { "00", "01", "02", "04", "05", "06", "14", "15", "16", "17", "20", "21", "22", "40", "41", "42", "44", "46", "60", "61", "62", "63", "F0", "08", "09", "0A", "0B", "0C", "0D", "0E", "0F", "18", "19", "1D", "38", "39", "CC", "DF" };


  

// GRUPOS


//////////////////////
string[] Grupo1_1 = new string[] {"80","81","82","83"};
 
string[] _MasMrMasImm8 = new string {"80","82","83"};
string[] _MasMrMasImm32 = new string {"81"};
string[] _66MasMrMasImm16 = new string {"81"};

/////////////////////




//////////           ***************************XOP POP

string[] Grupo1A_1 = new string[] {"8F"};

string[] _MasMr = new string {"8F/0"};   // POP Ev     RXB (mmmmm<8)=POP  (00000-00111-[01011-11111] reservado)  (01000 mapa 8) (01001 mapa 9) (A 01010 mapa 10)
string[] _XOP = new string {"8F/1_7"};   // INTEL ???    AMD Confirmado /1 /5

//  MAPA 8

string[] _XOPmas3masMRmasImm8_8pp00 = new string {"85","86","87","95","96","97","A2","A3","A6","B6","C0","C1","C2","C3","CC","CD","CE","CF","EC","ED","EE","EF","8E","8F","9E","9F"};

// MAPA 9

string[] _XOPmas3masMR_9pp00 = new string  {"80","81","82","83","90","91","92","93","94","95","96","97","C1","C2","C3","C6","C7","D1","D2","D3","D6","D7","E1","E2","E3"
,"98","99","9A","9B","CB","DB"};


string[] _XOPGRUPO_1_9pp00MasMR_01Rg = new string {"01","001","010","011","100","101","110","111"};

string[] _XOPGRUPO_2_9pp00MasMR_02Rg = new string {"02","001","110","111"};


string[] _XOPGRUPO_3_9pp00MasMRMod11_12Rg = new string {"12","000","001"};


string[] _XOPmas3masMRmasImm32_10pp00 = new string  {"10"};


string[] _XOPGRUPO_4_10pp00MasMRmasImm32Rg = new string {"12","000","001"};


////////////////////*************************fin XOP*****************************************************************************************************

string[] Grupo2_1 = new string[] {"C0","C1","D0","D1","D2","D3"};
 
string[] G2_1UnOpcodeMasMRMasImm8 = new string[] {"C0","C1"};
string[] G2_1UnOpcodeMasMR = new string["DD","D1","D2","D3"]


////////////////////////***************************************fin grupo2_1
////////////////////////////////////////////////************  GRUPO 3_1

string[] Grupo3_1 = new string[] {"F6","F7"};

string[] G3_1UnOpcodeMasMRMasImm8Rg = new string[] {"F6","000","001"};

string[] G3_1UnOpcodeMasMRRg = new string["F6","010","011","100","101","110","111"]

string[] G3_1UnOpcodeMasMRMasImm32Rg = new string[] {"F7","000","001"};
string[] G3_1_66_UnOpcodeMasMRMasImm16Rg = new string[] {"F7","000","001"};

string[] G3_1UnOpcodeMasMRRg = new string {"F7","010","011","100","101","110","111"};


//////////////////////*******************************************

/////////////////////*************************gRUPO 4_1
string[] Grupo4_1 = new string[] {"FE"};

string[] G4_1UnOpcodeMasMRRg = new string {"FE","000","001"}


////////////////////////***********************
//////////////////////////*************grupo 5_1

string[] Grupo5_1 = new string[] {"FF"};

string[] G5_1UnOpcodeMasMRRg = new string {"FF","000","001","010","011","100","101","110"}


////////////////////////***********************

////////////////////***********************GRUPO 6_2
string[] OFGrupo6_2 = new string[] {"00"};


string[] G6_2UnOpcodeMasMRRg = new string {"00","000","001","010","011","100","101"}


////////////////////****************************
////////////////////*****************************GRUPO 7_2
string[] OFGrupo7_2 = new string[] {"01"};


String[] G7_2_Mas_1_Solo_Mod11? = new string {"01","C1","C2","C3","C4","C8","C9","CA","CB","CF","D0","D1","D4","D5","D6","D7","F8","F9","D8","D9","DA","DB","DC","DD","DE","DF","FA","FB","FD","FE","FF"};


String[] G7_2_MasMRmod11No = new string {"01","000","001","010","011","100","110","111"};


//////////////////////*********************
//////////////////////****************************GRUPO 8_2

string[] OFGrupo8_2_OFBA = new string[] {"BA"};


String[] G8_2_MasMRmasImm8_0FBARg = new string {"100","101","110","111"};

///////////////////////*****************************
///////////////////////*****************GRUPO 9_2

string[] OFGrupo9_2_0FC7 = new string[] {"C7"};



String[] G9_2_MasMR_0FC7Rg = new string {"001","110","111"};



////////////////////////////////*****************************

/////////////////////////////////****************GRUPO 10_2   UD1
string[] OFGrupo10_2_OFB9 = new string[] {"B9"};


String[] G10_2_MasMR_0FB9_UD1 = new string {"B9"};



///////////////////////////////////******************************
///////////////////////////////////********************** GRUPO 11_1

string[] Grupo11_1 = new string[] {"C6","C7"};

String[] G11_1_MasMRmasImm8Rg = new string {"C6","000","111","F8"};
String[] G11_1_MasMRmasImm32Rg = new string {"C7","000","111","F8"};
String[] G11_1_MasMRmasImm16_66Rg = new string {"C7","000","111","F8"};




//////////////////////////////////************************

///////////////////////////////////****************************
GRUPO 12_2
string[] OFGrupo12_2 = new string[] {"71"};

String[] G12_2_MasMRmasImm8_OF71Rg = new string {"71","010","100","110"};


//////////////////////////////////****************************
///////////////////////////////////**************************GRUPO 13_2

string[] OFGrupo13_2 = new string[] {"72"};

String[] G13_2_MasMRmasImm8_OF72Rg = new string {"72","010","100","110"};

String[] G13_2_BLANCO_OF72Rg = new string {"000","001","011","101","111"};




//////////////////////////////////***************************

///////////////////////////////////**************************GRUPO 14_2

string[] OFGrupo14_2_0F73 = new string[] {"73"};

String[] G14_2_MasMRmasImm8_OF73Rg = new string {"73","010","011","110","111"};




//////////////////////////////////***************************
/////////////////////////////////**************************GRUPO 15_2

string[] OFGrupo15_2 = new string[] {"AE"};

String[] G14_2_MasMR_OFAE?Rg = new string {"AE","000","001","010","011","100","101","110","111"};  //



/////////////////////////////******************************
/////////////////////////////////**************************GRUPO 16_2

string[] OFGrupo16_2 = new string[] {"18"};

String[] G14_2_MasMR_OF18Rg = new string {"18","000","001","010","011"};





/////////////////////////////******************************
/////////////////////////////////**************************GRUPO 17_3

string[] OF38Grupo17_3_0F38 = new string[] {{"F3"};

String[] G14_2_MasMR_OF38?VEXRg = new string {"38","001","010","011"};


//////////////////////////////////******************************
/////////////////////////////////**************************GRUPO 17_2


string[] 66OFGrupo17_2_66OF = new string[] {{"78"};
                                  
String[] G17_2_MasMRmasImm8_Imm8_66OF = new string {"78","000"};



/////////////////////////////******************************
////////////////////////////****************************UD2_2  
string[] OFGrupoUD2_2 = new string[] {"0B"};

String[] G_UD2_2_SOLO_0F0B_UD2 = new string {"0B"};

/////////////////////////////*****************************
//////////////////////////////*************************************GRUPO PREFETCHW  Y FEMMS  ACTIVO EN LOS NUEVOS PROCESADORES

string[] OFGrupoP_2 = new string[] {"0D","0E"};


String[] GP_2_MasMR = new string {"0D","0E"};   //0D INTEL /1, AMD EL RESTO /0 ESCLUSIVE, /1 /3 MODIF   rESTO PREFETCH   OE FEMMS


/////////////////////////////////////////************************************************
/////////////////////////////////////******************************3D NOW  0F0F   ABANDONADO........

string[] OF3DNOW = new string[] {"OF"};

string[] OF0F3DNOWmasMRmasSIB?masDesplaz?masImm8?masOpcode = new string {"BF","9E","9A","AA","AE","90","A0","B0","94","A4","0D","1D" ,"96","97","B4","A6","A7","B6"
,"B7","00","01","02","03","04","05","06","07","10","11","12","13","14","15","16","17","20","21","22","23","24","25","26","27","30","31","32","33","40","41","42","43",
"44","45","46","50","51","52","53","54","56","57","86","87","90","94","96","97","0C","1C","8A","8E","9A","9E","BB"};

string[] OF0F3DNOW_BLANCO= new string {"16","17","34","35","36","37","47","6*","7*","80","81","82","83","84","85","91","92","93","95","A1","A2","A3","A5","B1","B2","B3"
,"B5","C*","D*","E*","F*","08","09","0A","0B","0E","0F","18","19","1A","1B","1E","1F","28","29","2A","2B","2C","2D","2E","2F","38","39","3A","3B","3C","3D","3E","3F","48","49"
,"4A","4B","4C","4D","4E","4F","58","59","5A","5B","5C","5D","5E","5F","88","89","8B","8C","8D","8F","98","99","9B","9C","9D","9F","A8","A9","AB","AC","AD","AF",
"B8","B9","BA","BC","BD","BE"};




///////////////////////////////////////////*****************************

////////////////////////////////////////**********************************VEX (C5  + Rvvvvlpp + opcodemap1)  (C4 + RXBmap + Wvvvvlpp + Opcodemap[1,2,3])

// MAPA 1

string[] Map1masMrpp00 = new string[] {"10","11","12","13","14","15","16","17","50","51","52","53","54","55","56","57","28","29","2B","2E","2F","58","59","5A","5B","5C","5D","5E","5F"};
string[] Map1masMrmasImm8pp00 = new string[] {"C2","C6"};
string[] Map1solopp00 = new string[] {"77"};
string[] Map1pp00blanco = new string[] {"60","61","62","63","64","65","66","67","70","71","72","73","74","75","76","A0","A1","A2","A3","A4","A5","A6","A7",
"B0","B1","B2","B3","B4","B5","B6","B7","C0","C1","C3","C4","C5","C7","D0","D1","D2","D3","D4","D5","D6","D7","E0","E1","E2","E3","E4","E5","E6","E7",
"F0","F1","F2","F3","F4","F5","F6","F7","18","19","1A","1B","1C","1D","1E","1F","2A","2C","2D","68","69","6A","6B","6C","6D","6E","6F","78","79","7A","7B"
,"7C","7D","7E","7F","C8","C9","CA","CB","CC","CD","CE","CF","D8","D9","DA","DB","DC","DD","DE","DF","E8","E9","EA","EB","EC","ED","EE","EF","F8","F9","FA","FB","FC","FD","FE","FF"};

string[] Map1masMrpp01 = new string[] {"10","11","12","13","14","15","16","17","50","51","54","55","56","57","60","61","62","63","64","65","66","67","74","75","76"
,"D0","D1","D2","D3","D4","D5","D6","D7","E0","E1","E2","E3","E4","E5","E6","E7","F1","F2","F3","F4","F5","F6","F7","28","29","2B","2E","2F",
"58","59","5A","5B","5C","5D","5E","5F","68","69","6A","6B","6C","6D","6E","6F","7C","7D","7E","7F","D8","D9","DA","DB","DC","DD","DE","DF","E8","E9","EA","EB","EC","ED","EE","EF",
"F8","F9","FA","FB","FC","FD","FE"};
string[] Map1masMrmasImm8pp01 = new string[] {"70","C2","C4","C5","C6"};
string[] Map1pp01blanco = new string[] {"52","53","77","A0","A1","A2","A3","A4","A5","A6","A7","B0","B1","B2","B3","B4","B5","B6","B7","C0","C1","C3","C7","F0",
"18","19","1A","1B","1C","1D","1E","1F","2A","2C","2D","78","79","7A","7B","C8","C9","CA","CB","CC","CD","CE","CF","FF"};

string[] Map1masMrpp10 = new string[] {"10","11","12","16","51","52","53","E6","2A","2C","2D","58","59","5A","5B","5C","5D","5E","5F","6F",
"7E","7F"};
string[] Map1masMrmasImm8pp10 = new string[] {"70","C2"};
string[] Map1pp10blanco = new string[] {"13","14","15","17","50","54","55","56","57","71","72","73","74","75","76","77","60","61","62","63","64","65","66","67"
"A0","A1","A2","A3","A4","A5","A6","A7","B0","B1","B2","B3","B4","B5","B6","B7","C0","C1","C3","C4","C5","C6","C7","D0","D1","D2","D3","D4","D5","D6","D7",
"E0","E1","E2","E3","E4","E5","E7","F0","F1","F2","F3","F4","F5","F6","F7","18","19","1A","1B","1C","1D","1E","1F","28","29","2B","2E","2F",
"68","69","6A","6B","6C","6D","6E","78","79","7A","7B","7C","7D","C8","C9","CA","CB","CC","CD","CE","CF","D8","D9","DA","DB","DC","DD","DE","DF","E8","E9","EA","EB","EC","ED","EE","EF",
"F8","F9","FA","FB","FC","FD","FE","FF"};

string[] Map1masMrpp11 = new string[] {"10","11","12","51","D0","E6","F0","2A","2C","2D","58","59","5A","5C","5D","5E","5F","7C","7D"};
string[] Map1masMrmasImm8pp11 = new string[] {"70","C2"};
string[] Map1pp11blanco = new string[] {"13","14","15","16","17","50","52","53","54","55","56","57","71","72","73","74","75","76","77","60","61","62","63","64","65","66"
,"67","A0","A1","A2","A3","A4","A5","A6","A7","B0","B1","B2","B3","B4","B5","B6","B7","C0","C1","C3","C4","C5","C6","C7","D1","D2","D3","D4","D5","D6","D7",
"E0","E1","E2","E3","E4","E5","E7","F1","F2","F3","F4","F5","F6","F7","18","19","1A","1B","1C","1D","1E","1F","28","29","2B","2E","2F","5B","68","69","6A","6B","6C","6D","6E","6F",
"78","79","7A","7B","7E","7F","C8","C9","CA","CB","CC","CD","CE","CF","D8","D9","DA","DB","DC","DD","DE","DF","E8","E9","EA","EB","EC","ED","EE","EF",
"F8","F9","FA","FB","FC","FD","FE","FF"};
string[] Map1_VEXgrupo12_01 = new string[] {"71"};
string[] Map1masMrmasImm8pp01_Mod_71 = new string[] {"010","100","110"};

string[] Map1_VEXgrupo13_01 = new string[] {"72"};

string[] Map1masMrmasImm8pp01_Mod_72 = new string[] {"010","100","110"};

string[] Map1_VEXgrupo14_01 = new string[] {"73"};

string[] Map1masMrmasImm8pp01_Mod_73 = new string[] {"010","011","110","111"};

string[] Map1_VEXgrupo15 = new string[] {"AE"};

string[] Map1masMrpp00_Mod_AE = new string[] {"010","011"};

/////////////////////////////////////******************************************
/////////////////////////////////////******************************************
// MAPA 2

string[] Map2masMrpp01 {"00","01","02","03","04","05","06","07","13","16","17","20","21","22","23","24","25","30","31","32","33","34","35","36","37","40","41","45","46","47",
"45","46","90","91","92","93","96","97","A6","A7","B6","B7","F5","F7","08","09","0A","0B","0C","0D","0E","0F","18","19","1A","1C","1D","1E","28","29","2A","2B","2C","2D","2E","2F",
"38","39","3A","3B","3C","3D","3E","3F","58","59","5A","78","79","8C","8E","98","99","9A","9B","9C","9D","9E","9F","A8","A9","AA","AB","AC","AD","AE","AF","B8","B9","BA","BB"
,"BC","BD","BE","BF","DB","DC","DD","DE","DF"};

string[] Map2masMrpp00 {"F2","F5","F7","F5","F7"};


string[] Map2_VEXgrupo17 = new string[] {"F3"};
string[] Map2masMrpp00_Mod_F3 = new string[] {"001","010","011"};


string[] Map2masMrpp10 {"F7"};

string[] Map2masMrpp11 {"F5","F6","F7"};



/////////////////////////////////////******************************************

/////////////////////////////////////******************************************IMM8
// MAPA 3

string[] Map3masMrMasImm8pp01 {"00","01","02","04","05","06","14","15","16","17","20","22","40","41","42","44","46","60","61","62","63","08","09","0A","0B","0C","0D","0E","0F","18",
"19","1D","38","39","DF"};
string[] Map3masMrpp01 {"21","48","49","4A","4B","4C","5C","5D","5E","5F","68","69","6A","6B","6C","6D","6E","6F","78","79","7A","7B","7C","7D","7E","7F"};
string[] Map3masMrMasImm8pp11 {"F0"};


/////////////////////////////////////******************************************



« Última modificación: 26 Julio 2020, 21:56 por FFernandez » En línea

FFernandez

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Mensajes: 44


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Re: Estructuras Binarias x86-64
« Respuesta #2 en: 22 Julio 2020, 22:32 »

Segundo:   Base de datos de Instrucciones Documentadas



AMD


37;NONE;NONE;OF=U-SF=U-ZF=U-AF=M-PF=U-CF=M;AAA; Create an unpacked BCD number. (Invalid in 64-bit mode.)
D5-0A;NONE;NONE;OF=U-SF=M-ZF=M-AF=U-PF=M-CF=U;AAD; Adjust two BCD digits in AL and AH. (Invalid in 64-bit mode.)
D5;NONE;ib;OF=U-SF=M-ZF=M-AF=U-PF=M-CF=U;(None); Adjust two BCD digits to the immediate byte base. (Invalid in 64-bit mode.)
D4-0A;NONE;NONE;OF=U-SF=M-ZF=M-AF=U-PF=M-CF=U;AAM; Create a pair of unpacked BCD values in AH and AL. (Invalid in 64-bit mode.)
D4;NONE;ib;OF=U-SF=M-ZF=M-AF=U-PF=M-CF=U;(None); reate a pair of unpacked values to the immediate byte base (Invalid in 64-bit mode.)
3F;NONE;NONE;OF=U-SF=U-ZF=U-AF=M-PF=U-CF=M;AAS; Create an unpacked BCD number from the contents ofthe AL register (Invalid in 64-bit mode.)
14;AL, imm8;ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm8 to AL + CF.
15;AX, imm16;iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm16 to AX + CF.
15;EAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm32 to EAX + CF.
15;RAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add sign-extended imm32 to RAX + CF.
80;reg/mem8, imm8;/2-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm8 to reg/mem8 + CF.
81;reg/mem16, imm16;/2-iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm16 to reg/mem16 + CF.
81;reg/mem32, imm32;/2-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add imm32 to reg/mem32 + CF.
81;reg/mem64, imm32;/2-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add sign-extended imm32 to reg/mem64 + CF.
83;reg/mem16, imm8;/2-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add sign-extended imm8 to reg/mem16 + CF.
83;reg/mem32, imm8;/2-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add sign-extended imm8 to reg/mem32 + CF.
83;reg/mem64, imm8;/2-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add sign-extended imm8 to reg/mem64 + CF.
10;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg8 to reg/mem8 + CF
11;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg16 to reg/mem16 + CF.
11;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg32 to reg/mem32 + CF.
11;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg64 to reg/mem64 + CF.
12;reg8, reg/mem8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg/mem8 to reg8 + CF.
13;reg16, reg/mem16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg/mem16 to reg16 + CF.
13;reg32, reg/mem32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg/mem32 to reg32 + CF.
13;reg64, reg/mem64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADC; Add reg/mem64 to reg64 + CF.
66-0F-38-F6;reg32, reg/mem32;/r;CF=M;ADCX; Unsigned add with carryflag
66-0F-38-F6;reg64, reg/mem64;/r;CF=M;ADCX; Unsigned add with carry flag.
04;AL, imm8;ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm8 to AL.
05;AX, imm16;iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm16 to AX.
05;EAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm32 to EAX.
05;RAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add sign-extended imm32 to RAX.
80;reg/mem8, imm8;/0-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm8 to reg/mem8.
81;reg/mem16, imm16;/0-iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm16 to reg/mem16
81;reg/mem32, imm32;/0-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add imm32 to reg/mem32.
81;reg/mem64, imm32;/0-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add sign-extended imm32 to reg/mem64.
83;reg/mem16, imm8;/0-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add sign-extended imm8 to reg/mem16
83;reg/mem32, imm8;/0-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add sign-extended imm8 to reg/mem32.
83;reg/mem64, imm8;/0-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add sign-extended imm8 to reg/mem64.
00;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg8 to reg/mem8.
01;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg16 to reg/mem16.
01;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg32 to reg/mem32.
01;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg64 to reg/mem64.
02;reg8, reg/mem8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg/mem8 to reg8.
03;reg16, reg/mem16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg/mem16 to reg16.
03;reg32, reg/mem32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg/mem32 to reg32.
03;reg64, reg/mem64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;ADD; Add reg/mem64 to reg64.
F3-0F-38-F6;reg32, reg/mem32;/r;OF=M;ADOX; Unsigned add with overflow flag
F3-0F-38-F6;reg64, reg/mem64;/r;OF=M;ADOX; Unsigned add with overflow flag.
24;AL, imm8;ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of AL with an immediate 8-bit value and store the result in AL.
25;AX, imm16;iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of AX with an immediate 16-bit value and store the result in AX.
25;EAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of EAX with an immediate 32-bit valueand store the result in EAX.
25;RAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of RAX with a sign-extended immediate 32-bit
20;reg/mem8, reg8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of an 8-bit register or memory location with the contents of an 8-bit register.
21;reg/mem16, reg16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 16-bit register or memory location with the contents of a 16-bit register.
21;reg/mem32, reg32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 32-bit register or memory location with the contents of a 32-bit register.
21;reg/mem64, reg64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 64-bit register or memory location with the contents of a 64-bit register.
22;reg8, reg/mem8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of an 8-bit register with the contents of an 8-bit memory location or register.
23;reg16, reg/mem16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 16-bit register with the contents of a 16-bit memory location or register.
23;reg32, reg/mem32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 32-bit register with the contents of a 32-bit memory location or register.
23;reg64, reg/mem64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;AND; and the contents of a 64-bit register with the contents of a 64-bit memory location or register.
C4-RXB.02-0.src1.0.00-F2;reg32, reg32, reg/mem32;/r;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=0;ANDN; Logical And-Not
;reg64, reg64, reg/mem64;NONE;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=0;ANDN;  Logical And-Not
C4-RXB.02-0.cntl.0.00-F7;reg32, reg/mem32, reg32;/r;OF=0-SF=U-ZF=M-AF=U-PF=U-CF=0;BEXTR; (register form) Bit Field Extract
C4-RXB.02-1.cntl.0.00-F7;reg64, reg/mem64, reg64;/r;OF=0-SF=U-ZF=M-AF=U-PF=U-CF=0;BEXTR; (register form) Bit Field Extract
8F-RXB.0A-0.1111.0.00-10;reg32, reg/mem32, imm32;/r-id;OF=0-SF=U-ZF=M-AF=U-PF=U-CF=0;BEXTR; (immediate form) Bit Field Extract
8F-RXB.0A-1.1111.0.00-10;reg64, reg/mem64, imm32;/r-id;OF=0-SF=U-ZF=M-AF=U-PF=U-CF=0;BEXTR; (immediate form) Bit Field Extract
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCFILL; Fill From Lowest Clear Bit
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCFILL; Fill From Lowest Clear Bit
8F-RXB.09-0.dest.0.00-02;reg32, reg/mem32;/6;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCI; Isolate Lowest Clear Bit
8F-RXB.09-1.dest.0.00-02;reg64, reg/mem64;/6;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCI; Isolate Lowest Clear Bit
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/5;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCIC; Isolate Lowest Clear Bit and Complement
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/5;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCIC; Isolate Lowest Clear Bit and Complement
8F-RXB.09-0.dest.0.00-02;reg32, reg/mem32;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCMSK; Mask From Lowest Clear Bit
8F-RXB.09-1.dest.0.00-02;reg64, reg/mem64;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCMSK; Mask From Lowest Clear Bit
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/3;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCS; Set Lowest Clear Bit
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/3;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLCS; Set Lowest Clear Bit
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/2;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSFILL; Fill From Lowest Set Bit
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/2;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSFILL; Fill From Lowest Set Bit
C4-RXB.02-0.dest.0.00-F3;reg32, reg/mem32;/3;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSI; Isolate Lowest Set Bit
C4-RXB.02-1.dest.0.00-F3;reg64, reg/mem64;/3;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSI; Isolate Lowest Set Bit
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/6;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSIC; Isolate Lowest Set Bit and Complement
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/6;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSIC; Isolate Lowest Set Bit and Complement
C4-RXB.02-0.dest.0.00-F3;reg32, reg/mem32;/2;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSMSK; Mask From Lowest Set Bit
C4-RXB.02-1.dest.0.00-F3;reg64, reg/mem64;/2;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSMSK; Mask From Lowest Set Bit
C4-RXB.02-0.dest.0.00-F3;reg32, reg/mem32;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSR; Reset Lowest Set Bit
C4-RXB.02-1.dest.0.00-F3;reg64, reg/mem64;/1;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BLSR; Reset Lowest Set Bit
62;reg16, mem16&mem16;/r;NONE;BOUND; Test whether a 16-bit array index is within the bounds specified by the two 16-bit values in mem16&mem16. (Invalid in 64-bit mode.)
62;reg32, mem32&mem32;/r;NONE;BOUND; Test whether a 32-bit array index is within the bounds specified by the two 32-bit values in mem32&mem32. (Invalid in 64-bit mode.)
0F-BC;reg16, reg/mem16;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSF; Bit scan forward on the contents of reg/mem16.
0F-BC;reg32, reg/mem32;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSF; Bit scan forward on the contents of reg/mem32.
0F-BC;reg64, reg/mem64;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSF; Bit scan forward on the contents of reg/mem64
0F-BD;reg16, reg/mem16;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSR; Bit scan reverse on the contents of reg/mem16.
0F-BD;reg32, reg/mem32;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSR; Bit scan reverse on the contents of reg/mem32.
0F-BD;reg64, reg/mem64;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=U;BSR; Bit scan reverse on the contents of reg/mem64.
0F-C8;reg32;+rd;NONE;BSWAP; Reverse the byte order of reg32.
0F-C8;reg64;+rq;NONE;BSWAP; Reverse the byte order of reg64.
0F-A3;reg/mem16, reg16;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-A3;reg/mem32, reg32;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-A3;reg/mem64, reg64;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-BA;reg/mem16, imm8;/4-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-BA;reg/mem32, imm8;/4-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-BA;reg/mem64, imm8;/4-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BT; Copy the value of the selected bit to the carry flag.
0F-BB;reg/mem16, reg16;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-BB;reg/mem32, reg32;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-BB;reg/mem64, reg64;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-BA;reg/mem16, imm8;/7-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-BA;reg/mem32, imm8;/7-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-BA;reg/mem64, imm8;/7-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTC; Copy the value of the selected bit to the carry flag, then complement the selected bit.
0F-B3;reg/mem16, reg16;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-B3;reg/mem32, reg32;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-B3;reg/mem64, reg64;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-BA;reg/mem16, imm8;/6-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-BA;reg/mem32, imm8;/6-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-BA;reg/mem64, imm8;/6-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTR; Copy the value of the selected bit to the carry flag, then clear the selected bit
0F-AB;reg/mem16, reg16;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
0F-AB;reg/mem32, reg32;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
0F-AB;reg/mem64, reg64;/r;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
0F-BA;reg/mem16, imm8;/5-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
0F-BA;reg/mem32, imm8;/5-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
0F-BA;reg/mem64, imm8;/5-ib;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=M;BTS; Copy the value of the selected bit to the carry flag, then set the selected bit
C4-RXB.02-0.index.0.00-F5;reg32, reg/mem32, reg32;/r;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BZHI; Zero High Bits
C4-RXB.02-1.index.0.00-F5;reg64, reg/mem64, reg64;/r;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;BZHI; Zero High Bits
E8;rel16off;iw;NONE;CALL_Near; Near call with the target specified by a 16-bit relative displacement
E8;rel32off;id;NONE;CALL_Near; Near call with the target specified by a 32-bit relative displacement
FF;reg/mem16;/2;NONE;CALL_Near; Near call with the target specified by reg/mem16.
FF;reg/mem32;/2;NONE;CALL_Near; Near call with the target specified by reg/mem32. (There is no prefix for encoding this in 64-bit mode.)
FF;reg/mem64;/2;NONE;CALL_Near; Near call with the target specified by reg/mem64.
9A;pntr16:16;cd;NONE;CALL_FAR; Far call direct, with the target specified by a far pointer contained in the instruction. (Invalid in 64-bit mode.)
9A;pntr16:32;cp;NONE;CALL_FAR; Far call direct, with the target specified by a far pointer contained in the instruction. (Invalid in 64-bit mode.)
FF;mem16:16;/3;NONE;CALL_FAR; Far call indirect, with the target specified by a far pointer in memory
FF;mem16:32;/3;NONE;CALL_FAR; Far call indirect, with the target specified by a far pointer in memory
98;NONE;NONE;NONE;CBW; Sign-extend AL into AX.
98;NONE;NONE;NONE;CWDE; Sign-extend AX into EAX.
98;NONE;NONE;NONE;CDQE; Sign-extend EAX into RAX.
99;NONE;NONE;NONE;CWD; Sign-extend AX into DX:AX.
99;NONE;NONE;NONE;CDQ; Sign-extend EAX into EDX:EAX.
99;NONE;NONE;NONE;CQO; Sign-extend RAX into RDX:RAX.
F8;NONE;NONE;CF=0;CLC; Clear the carry flag (CF) to zero.
FC;NONE;NONE;DF=0;CLD; Clear the direction flag (DF) to zero.
0F-AE;mem8;/7;NONE;CLFLUSH; flush cache line containing mem8.
66-0F-AE;mem8;/7;NONE;CLFLUSHOPT; Flush cache line containing mem8
66-0F-AE;NONE;/6;;CLWB; Cache line write-back.
0F-01-FC;rAX;NONE;NONE;CLZERO; Clears cache line containing rAX
F5;NONE;NONE;CF=M;CMC; Complement the carry flag (CF).
0F-40;reg16, reg/mem16;/r;NONE;CMOVO; Move if overflow (OF = 1).
0F-40; reg32, reg/mem32;/r;NONE;CMOVO; Move if overflow (OF = 1).
0F-40; reg64, reg/mem64;/r;NONE;CMOVO; Move if overflow (OF = 1).
0F-41;reg16, reg/mem16;/r;NONE;CMOVNO; Move if not overflow (OF = 0).
0F-41;reg32, reg/mem32;/r;NONE;CMOVNO; Move if not overflow (OF = 0).
0F-41;reg64, reg/mem64;/r;NONE;CMOVNO; Move if not overflow (OF = 0).
0F-42;reg16, reg/mem16;/r;NONE;CMOVB; Move if below (CF = 1).
0F-42;reg32, reg/mem32;/r;NONE;CMOVB; Move if below (CF = 1).
0F-42; reg64, reg/mem64;/r;NONE;CMOVB; Move if below (CF = 1).
0F-42;reg16, reg/mem16;/r;NONE;CMOVC; Move if below (CF = 1).
0F-42;reg32, reg/mem32;/r;NONE;CMOVC; Move if below (CF = 1).
0F-42; reg64, reg/mem64;/r;NONE;CMOVC; Move if below (CF = 1).
0F-42;reg16, reg/mem16;/r;NONE;CMOVNAE; Move if not above or equal (CF = 1).
0F-42;reg32, reg/mem32;/r;NONE;CMOVNAE; Move if not above or equal (CF = 1).
0F-42;reg64, reg/mem64;/r;NONE;CMOVNAE; Move if not above or equal (CF = 1).
0F-43;reg16,reg/mem16;/r;NONE;CMOVNB; Move if not below (CF = 0).
0F-43;reg32,reg/mem32;/r;NONE;CMOVNB; Move if not below (CF = 0).
0F-43;reg64,reg/mem64;/r;NONE;CMOVNB; Move if not below (CF = 0).
0F-43;reg16,reg/mem16;/r;NONE;CMOVNC; Move if not carry (CF = 0).
0F-43;reg32,reg/mem32;/r;NONE;CMOVNC; Move if not carry (CF = 0).
0F-43;reg64,reg/mem64;/r;NONE;CMOVNC; Move if not carry (CF = 0).
0F-43;reg16, reg/mem16;/r;NONE;CMOVAE; Move if above or equal (CF = 0).
0F-43; reg32, reg/mem32;/r;NONE;CMOVAE; Move if above or equal (CF = 0).
0F-43; reg64, reg/mem64;/r;NONE;CMOVAE; Move if above or equal (CF = 0).
0F-44;reg16, reg/mem16;/r;NONE;CMOVZ; Move if equal (ZF =1).
0F-44;reg32, reg/mem32;/r;NONE;CMOVZ; Move if equal (ZF =1).
0F-44; reg64, reg/mem64;/r;NONE;CMOVZ; Move if equal (ZF =1).
0F-44;reg16, reg/mem16;/r;NONE;CMOVE; Move if equal (ZF =1).
0F-44;reg32, reg/mem32;/r;NONE;CMOVE; Move if equal (ZF =1).
0F-44; reg64, reg/mem64;/r;NONE;CMOVE; Move if equal (ZF =1).
0F-45;reg16, reg/mem16;/r;NONE;CMOVNZ; Move if not zero (ZF = 0).
0F-45;reg32, reg/mem32;/r;NONE;CMOVNZ; Move if not zero (ZF = 0).
0F-45; reg64, reg/mem64;/r;NONE;CMOVNZ; Move if not zero (ZF = 0).
0F-45;reg16, reg/mem16;/r;NONE;CMOVNE; Move if not equal (ZF = 0).
0F-45;reg32, reg/mem32;/r;NONE;CMOVNE; Move if not equal (ZF = 0).
0F-45; reg64, reg/mem64;/r;NONE;CMOVNE; Move if not equal (ZF = 0).
0F-46;reg16, reg/mem16;/r;NONE;CMOVBE; Move if below or equal (CF = 1 or ZF = 1).
0F-46;reg32, reg/mem32;/r;NONE;CMOVBE; Move if below or equal (CF = 1 or ZF = 1).
0F-46; reg64, reg/mem64;/r;NONE;CMOVBE; Move if below or equal (CF = 1 or ZF = 1).
0F-46;reg16, reg/mem16;/r;NONE;CMOVNA; Move if not above (CF = 1 or ZF = 1).
0F-46;reg32, reg/mem32;/r;NONE;CMOVNA; Move if not above (CF = 1 or ZF = 1).
0F-46;reg64, reg/mem64;/r;NONE;CMOVNA; Move if not above (CF = 1 or ZF = 1).
0F-47;reg16, reg/mem16;/r;NONE;CMOVNBE; Move if not below or equal (CF = 0 and ZF = 0).
0F-47;reg32,reg/mem32;/r;NONE;CMOVNBE; Move if not below or equal (CF = 0 and ZF = 0).
0F-47;reg64,reg/mem64;/r;NONE;CMOVNBE; Move if not below or equal (CF = 0 and ZF = 0).
0F-47;reg16, reg/mem16;/r;NONE;CMOVA; Move if above (CF = 0 and ZF = 0).
0F-47;reg32, reg/mem32;/r;NONE;CMOVA; Move if above (CF = 0 and ZF = 0).
0F-47;reg64, reg/mem64;/r;NONE;CMOVA; Move if above (CF = 0 and ZF = 0).
0F-48;reg16, reg/mem16;/r;NONE;CMOVS; Move if sign (SF =1).
0F-48;reg32, reg/mem32;/r;NONE;CMOVS; Move if sign (SF =1).
0F-48; reg64, reg/mem64;/r;NONE;CMOVS; Move if sign (SF =1).
0F-49;reg16, reg/mem16;/r;NONE;CMOVNS; Move if not sign (SF = 0).
0F-49;reg32, reg/mem32;/r;NONE;CMOVNS; Move if not sign (SF = 0).
0F-49;reg64, reg/mem64;/r;NONE;CMOVNS; Move if not sign (SF = 0).
0F-4A;reg16, reg/mem16;/r;NONE;CMOVP; Move if parity (PF = 1).
0F-4A;reg32, reg/mem32;/r;NONE;CMOVP; Move if parity (PF = 1).
0F-4A;reg64, reg/mem64;/r;NONE;CMOVP; Move if parity (PF = 1).
0F-4A;reg16, reg/mem16;/r;NONE;CMOVPE; Move if parity even (PF = 1).
0F-4A;reg32, reg/mem32;/r;NONE;CMOVPE; Move if parity even (PF = 1).
0F-4A; reg64, reg/mem64;/r;NONE;CMOVPE; Move if parity even (PF = 1).
0F-4B;reg16, reg/mem16;/r;NONE;CMOVNP; Move if not parity (PF = 0).
0F-4B;reg32, reg/mem32;/r;NONE;CMOVNP; Move if not parity (PF = 0).
0F-4B; reg64, reg/mem64;/r;NONE;CMOVNP; Move if not parity (PF = 0).
0F-4B;reg16, reg/mem16;/r;NONE;CMOVPO; Move if parity odd (PF = 0).
0F-4B;reg32, reg/mem32;/r;NONE;CMOVPO; Move if parity odd (PF = 0).
0F-4B; reg64, reg/mem64;/r;NONE;CMOVPO; Move if parity odd (PF = 0).
0F-4C;reg16, reg/mem16;/r;NONE;CMOVL; Move if less (SF <> OF).
0F-4C;reg32, reg/mem32;/r;NONE;CMOVL; Move if less (SF <> OF).
0F-4C;reg64, reg/mem64;/r;NONE;CMOVL; Move if less (SF <> OF).
0F-4C;reg16, reg/mem16;/r;NONE;CMOVNGE; Move if not greater or equal (SF <> OF).
0F-4C;reg32, reg/mem32;/r;NONE;CMOVNGE; Move if not greater or equal (SF <> OF).
0F-4C;reg64, reg/mem64;/r;NONE;CMOVNGE; Move if not greater or equal (SF <> OF).
0F-4D;reg16, reg/mem16;/r;NONE;CMOVNL; Move if not less (SF = OF).
0F-4D;reg32, reg/mem32;/r;NONE;CMOVNL; Move if not less (SF = OF).
0F-4D;reg64, reg/mem64;/r;NONE;CMOVNL; Move if not less (SF = OF).
0F-4D;reg16, reg/mem16;/r;NONE;CMOVGE; Move if greater or equal (SF = OF).
0F-4D;reg32, reg/mem32;/r;NONE;CMOVGE; Move if greater or equal (SF = OF).
0F-4D; reg64, reg/mem64;/r;NONE;CMOVGE; Move if greater or equal (SF = OF).
0F-4E;reg16, reg/mem16;/r;NONE;CMOVLE; Move if less or equal (ZF = 1 or SF <> OF).
0F-4E;reg32, reg/mem32;/r;NONE;CMOVLE; Move if less or equal (ZF = 1 or SF <> OF).
0F-4E;reg64, reg/mem64;/r;NONE;CMOVLE; Move if less or equal (ZF = 1 or SF <> OF).
0F-4E;reg16, reg/mem16;/r;NONE;CMOVNG; Move if not greater (ZF = 1 or SF <> OF).
0F-4E;reg32, reg/mem32;/r;NONE;CMOVNG; Move if not greater (ZF = 1 or SF <> OF).
0F-4E;reg64, reg/mem64;/r;NONE;CMOVNG; Move if not greater (ZF = 1 or SF <> OF).
0F-4F;reg16, reg/mem16;/r;NONE;CMOVNLE; Move if not less or equal (ZF = 0 and SF = OF).
0F-4F;reg32, reg/mem32;/r;NONE;CMOVNLE; Move if not less or equal (ZF = 0 and SF = OF).
0F-4F;reg64, reg/mem64;/r;NONE;CMOVNLE; Move if not less or equal (ZF = 0 and SF = OF).
0F-4F;reg16, reg/mem16;/r;NONE;CMOVG; Move if greater (ZF = 0 and SF = OF).
0F-4F;reg32, reg/mem32;/r;NONE;CMOVG; Move if greater (ZF = 0 and SF = OF).
0F-4F;reg64, reg/mem64;/r;NONE;CMOVG; Move if greater (ZF = 0 and SF = OF).
3C;AL, imm8;ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare an 8-bit immediate value with the contents of the AL register.
3D;AX, imm16;iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP;Compare a 16-bit immediate value with the contents of
3D;EAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP;Compare a 32-bit immediate value with the contents of
3D;RAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP;Compare a 32-bit immediate value with the contents of
80;reg/mem8, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare an 8-bit immediate value with the contents of an 8-bit register or memory operand.
81;reg/mem16, imm16;/7-iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare a 16-bit immediate value with the contents of a 16-bit register or memory operand.
81;reg/mem32, imm32;/7-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare a 32-bit immediate value with the contents of a 32-bit register or memory operand.
81;reg/mem64, imm32;/7-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare a 32-bit signed immediate value with the contents of a 64-bit register or memory operand.
83;reg/mem16, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare an 8-bit signed immediate value with the contents of a 16-bit register or memory operand.
83;reg/mem32, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare an 8-bit signed immediate value with the contents of a 32-bit register or memory operand.
83;reg/mem64, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare an 8-bit signed immediate value with the contents of a 64-bit register or memory operand.
38;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of an 8-bit register or memory operand with the contents of an 8-bit register.
39;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 16-bit register or memory operand with the contents of a 16-bit register.
39;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 32-bit register or memory operand with the contents of a 32-bit register.
39;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 64-bit register or memory operand with the contents of a 64-bit register.
3A;reg8, reg/mem8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of an 8-bit register with the contents of an 8-bit register or memory operand.
3B;reg16, reg/mem16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 16-bit register with the contents of a 16-bit register or memory operand.
3B;reg32, reg/mem32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 32-bit register with the contents of a 32-bit register or memory operand.
3B;reg64, reg/mem64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMP; Compare the contents of a 64-bit register with the contents of a 64-bit register or memory operand.
A6;mem8, mem8;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPS; Compare the byte at DS:rSI with the byte at ES:rDI and then increment or decrement rSI and rDI.
A7;mem16, mem16;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPS; Compare the word at DS:rSI with the word at ES:rDI and then increment or decrement rSI and rDI.
A7;mem32, mem32;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPS; Compare the doubleword at DS:rSI with the doubleword at ES:rDI and then increment or decrement rSI and rDI.
A7;mem64, mem64;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPS; Compare the quadword at DS:rSI with the quadword at ES:rDI and then increment or decrement rSI and rDI.
A6;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPSB; Compare the byte at DS:rSI with the byte at ES:rDI and then increment or decrement rSI and rDI.
A7;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPSW; Compare the word at DS:rSI with the word at ES:rDI and then increment or decrement rSI and rDI.
A7;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPSD; Compare the doubleword at DS:rSI with the doubleword at ES:rDI and then increment or decrement rSI and rDI.
A7;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPSQ; Compare the quadword at DS:rSI with the quadword at ES:rDI and then increment or decrement rSI and rDI.
0F-B0;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPXCHG; Compare AL register with an 8-bit register or memory location. If equal, copy the second operand to the first operand. Otherwise, copy the first operand to AL.
0F-B1;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPXCHG; Compare AX register with a 16-bit register or memory location. If equal, copy the second operand to the first operand. Otherwise, copy the first operand to AX.
0F-B1;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPXCHG; Compare EAX register with a 32-bit register or memory location. If equal, copy the second operand to the first operand. Otherwise, copy the first operand to EAX.
0F-B1;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;CMPXCHG; Compare RAX register with a 64-bit register or memory location. If equal, copy the second operand to the first operand. Otherwise, copy the first operand to RAX.
0F-C7;mem64;/1-m64;ZF=M;CMPXCHG8B; Compare EDX:EAX register to 64-bit memory location. If equal, set the zero flag (ZF) to 1 and copy the ECX:EBX register to the memory location. Otherwise, copy the memory location to EDX:EAX and clear the zero flag.
0F-C7;mem128;/1-m128;ZF=M;CMPXCHG16B; Compare RDX:RAX register to 128-bit memory location. If equal, set the zero flag (ZF) to 1 and copy the RCX:RBX register to the memory location. Otherwise, copy the memory location to RDX:RAX and clear the zero flag.
0F-A2;NONE;NONE;NONE;CPUID; Returns information about the processor and its capabilities. EAX specifies the function number, and the data is returned in EAX, EBX, ECX, EDX
F2-0F-38-F0;reg32, reg/mem8;/r;NONE;CRC32; Perform CRC32 operation on 8-bit values
F2-REX-0F-38-F0;reg32, reg/mem8;/r;NONE;CRC32; Encoding using REX prefix allows access to GPR8-15
F2-0F-38-F1;reg32, reg/mem16;/r;NONE;CRC32; Effective operand size determines size of second operand.
F2-0F-38-F1;reg32, reg/mem32;/r;NONE;CRC32; Effective operand size determines size of second operand.
F2-REX.W-0F-38-F0;reg64, reg/mem8;/r;NONE;CRC32; REX.W = 1.
F2-REX.W-0F-38-F1;reg64, reg/mem64;/r;NONE;CRC32; REX.W = 1.
27;NONE;NONE;OF=U-SF=M-ZF=M-AF=M-PF=M-CF=M;DAA; Decimal adjust AL. (Invalid in 64-bit mode.)
2F;NONE;NONE;OF=U-SF=M-ZF=M-AF=M-PF=M-CF=M;DAS; Decimal adjusts AL after subtraction. (Invalid in 64-bit mode.)
FE;reg/mem8;/1;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of an 8-bit register or memory location by 1
FF;reg/mem16;/1;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of a 16-bit register or memory location by 1
FF;reg/mem32;/1;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of a 32-bit register or memory location by 1
FF;reg/mem64;/1;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of a 64-bit register or memory location by 1
48;reg16;+rw;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of a 16-bit register by 1. (See “REX Prefix” on page 14.)
48;reg32;+rd;OF=M-SF=M-ZF=M-AF=M-PF=M;DEC; Decrement the contents of a 32-bit register by 1. (See “REX Prefix” on page 14.)
F6;reg/mem8;/6;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;DIV; Perform unsigned division of AX by the contents of an 8-bit register or memory location and store the quotient in AL and the remainder in AH.
F7;reg/mem16;/6;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;DIV; Perform unsigned division of DX:AX by the contents of a 16-bit register or memory operand store the quotient in AX and the remainder in DX.
F7;reg/mem32;/6;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;DIV; Perform unsigned division of EDX:EAX by the contents of a 32-bit register or memory location and store the quotient in EAX and the remainder in EDX.
F7;reg/mem64;/6;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;DIV; Perform unsigned division of RDX:RAX by the contents of a 64-bit register or memory location and store the quotient in RAX and the remainder in RDX.
C8-00;imm16, 0;iw;NONE;ENTER; Create a procedure stack frame.
C8-01;imm16, 1;iw;NONE;ENTER; Create a nested stack frame for a procedure.
C8;imm16, imm8;iw-ib;NONE;ENTER; Create a nested stack frame for a procedure.
F6;reg/mem8;/7;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;IDIV; Perform signed division of AX by the contents of an 8-bit register or memory location and store the quotient in AL and the remainder in AH.
F7;reg/mem16;/7;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;IDIV; Perform signed division of DX:AX by the contents of a 16-bit register or memory location and store the quotient in AX and the remainder in DX.
F7;reg/mem32;/7;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;IDIV; Perform signed division of EDX:EAX by the contents of a 32-bit register or memory location and store the quotient in EAX and the remainder in EDX.
F7;reg/mem64;/7;OF=U-SF=U-ZF=U-AF=U-PF=U-CF=U;IDIV; Perform signed division of RDX:RAX by the contents of a 64-bit register or memory location and store the quotient in RAX and the remainder in RDX.
F6;reg/mem8;/5;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of AL by the contents of an 8-bit memory or register operand and put the signed result in AX.
F7;reg/mem16;/5;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of AX by the contents of a 16-bit memory or register operand and put the signed result in DX:AX.
F7;reg/mem32;/5;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of EAX by the contents of a 32-bit memory or register operand and put the signed result in EDX:EAX.
F7;reg/mem64;/5;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of RAX by the contents of a 64-bit memory or register operand and put the signed result in RDX:RAX.
0F-AF;reg16, reg/mem16;/r;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 16-bit destination register by the contents of a 16-bit register or memory operand and put the signed result in the 16-bit destination register.
0F-AF;reg32, reg/mem32;/r;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 32-bit destination register by the contents of a 32-bit register or memory operand and put the signed result in the 32-bit destination register.
0F-AF;reg64, reg/mem64;/r;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 64-bit destination register by the contents of a 64-bit register or memory operand and put the signed result in the 64-bit destination register.
6B;reg16, reg/mem16, imm8;/r-ib;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 16-bit register or memory operand by a sign-extended immediate byte and put the signed result in the 16-bit destination register.
6B;reg32, reg/mem32, imm8;/r-ib;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 32-bit register or memory operand by a sign-extended immediate byte and put the signed result in the 32-bit destination register.
6B;reg64, reg/mem64, imm8;/r-ib;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 64-bit register or memory operand by a sign-extended immediate byte and put the signed result in the 64-bit destination register.
69;reg16, reg/mem16, imm16;/r-iw;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 16-bit register or memory operand by a sign-extended immediate word and put the signed result in the 16-bit destination register.
69;reg32, reg/mem32, imm32;/r-id;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 32-bit register or memory operand by a sign-extended immediate double and put the signed result in the 32-bit destination register.
69;reg64, reg/mem64, imm32;/r-id;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;IMUL; Multiply the contents of a 64-bit register or memory operand by a sign-extended immediate double and put the signed result in the 64-bit destination register.
E4;AL, imm8;ib;NONE;IN; Input a byte from the port at the address specified by imm8 and put it into the AL register.
E5;AX, imm8;ib;NONE;IN; Input a word from the port at the address specified by imm8 and put it into the AX register.
E5;EAX, imm8;ib;NONE;IN; Input a doubleword from the port at the address specified by imm8 and put it into the EAX register.
EC;AL, DX;NONE;NONE;IN; Input a byte from the port at the address specified by the DX register and put it into the AL register.
ED;AX, DX;NONE;NONE;IN; Input a word from the port at the address specified by the DX register and put it into the AX register.
ED;EAX, DX;NONE;NONE;IN; Input a doubleword from the port at the address specified by the DX register and put it into the EAX register.
FE;reg/mem8;/0;OF=M-SF=M-ZF=M-AF=M-PF=M;INC; Increment the contents of an 8-bit register or memory location by 1
FF;reg/mem16;/0;OF=M-SF=M-ZF=M-AF=M-PF=M;INC; Increment the contents of a 16-bit register or memory location by 1
FF;reg/mem32;/0;OF=M-SF=M-ZF=M-AF=M-PF=M;INC; Increment the contents of a 32-bit register or memory location by 1
FF;reg/mem64;/0;OF=M-SF=M-ZF=M-AF=M-PF=M;INC; Increment the contents of a 64-bit register or memory location by 1
40;reg16;+rw;OF=M-SF=M-ZF=M-AF=M-PF=M;INC;  Increment the contents of a 16-bit register by 1. (These opcodes are used as REX prefixes in 64-bit mode. See “REX Prefix” on page 14.)
40;reg32;+rd;OF=M-SF=M-ZF=M-AF=M-PF=M;INC; Increment the contents of a 32-bit register by 1. (These opcodes are used as REX prefixes in 64-bit mode. See “REX Prefix” on page 14.)
6C;mem8, DX;NONE;NONE;INS; Input a byte from the port specified by DX, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
6D;mem16, DX;NONE;NONE;INS; Input a word from the port specified by DX register, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
6D;mem32, DX;NONE;NONE;INS; Input a doubleword from the port specified by DX, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
6C;NONE;NONE;NONE;INSB; Input a byte from the port specified by DX, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
6D;NONE;NONE;NONE;INSW; Input a word from the port specified by DX, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
6D;NONE;NONE;NONE;INSD; Input a doubleword from the port specified by DX, put it into the memory location specified in ES:rDI, and then increment or decrement rDI.
CD;imm8;ib;VIF=M-AC=M-VM=M-RF=0-NT=M-IF=M-TF=0;INT; Call interrupt service routine specified by interrupt vector imm8 zero-extended to 64 bits.
CE;NONE;NONE;VIF=M-AC=M-VM=M-RF=0-NT=M-IF=M-TF=0;INTO; Call overflow exception if the overflow flag is set. (Invalid in 64-bit mode.)
70;rel8off;cb;NONE;JO; Jump if overflow (OF = 1).
0F-80;rel16off;cw;NONE;JO; Jump if overflow (OF = 1).
0F-80;rel32off;cd;NONE;JO; Jump if overflow (OF = 1).
71;rel8off;cb;NONE;JNO; Jump if not overflow (OF = 0).
0F-81;rel16off;cw;NONE;JNO; Jump if not overflow (OF = 0).
0F-81;rel32off;cd;NONE;JNO; Jump if not overflow (OF = 0).
72;rel8off;cb;NONE;JB; Jump if below (CF = 1).
0F-82;rel16off;cw;NONE;JB; Jump if below (CF = 1).
0F-82;rel32off;cd;NONE;JB; Jump if below (CF = 1).
72;rel8off;cb;NONE;JC; Jump if carry (CF = 1).
0F-82;rel16off;cw;NONE;JC; Jump if carry (CF = 1).
0F-82;rel32off;cd;NONE;JC; Jump if carry (CF = 1).
72;rel8off;cb;NONE;JNAE; Jump if not above or equal (CF = 1).
0F-82;rel16off;cw;NONE;JNAE; Jump if not above or equal (CF = 1).
0F-82;rel32off;cd;NONE;JNAE; Jump if not above or equal (CF = 1).
73;rel8off;cb;NONE;JNB; Jump if not below (CF = 0).
0F-83;rel16off;cw;NONE;JNB; Jump if not below (CF = 0).
0F-83;rel32off;cd;NONE;JNB; Jump if not below (CF = 0).
73;rel8off;cb;NONE;JNC; Jump if not carry (CF = 0).
0F-83;rel16off;cw;NONE;JNC; Jump if not carry (CF = 0).
0F-83;rel32off;cd;NONE;JNC; Jump if not carry (CF = 0).
73;rel8off;cb;NONE;JAE; Jump if above or equal (CF = 0).
0F-83;rel16off;cw;NONE;JAE; Jump if above or equal (CF = 0).
0F-83;rel32off;cd;NONE;JAE; Jump if above or equal (CF = 0).
74;rel8off;cb;NONE;JZ; Jump if zero (ZF = 1).
0F-84;rel16off;cw;NONE;JZ; Jump if zero (ZF = 1).
0F-84;rel32off;cd;NONE;JZ; Jump if zero (ZF = 1).
74;rel8off;cb;NONE;JE; Jump if equal (ZF = 1).
0F-84;rel16off;cw;NONE;JE; Jump if equal (ZF = 1).
0F-84;rel32off;cd;NONE;JE; Jump if equal (ZF = 1).
75;rel8off;cb;NONE;JNZ; Jump if not zero (ZF = 0).
0F-85;rel16off;cw;NONE;JNZ; Jump if not zero (ZF = 0).
0F-85;rel32off;cd;NONE;JNZ; Jump if not zero (ZF = 0).
75;rel8off;cb;NONE;JNE; Jump if not equal (ZF = 0).
0F-85;rel16off;cw;NONE;JNE; Jump if not equal (ZF = 0).
0F-85;rel32off;cd;NONE;JNE; Jump if not equal (ZF = 0).
76;rel8off;cb;NONE;JBE; Jump if below or equal (CF = 1 or ZF = 1).
0F-86;rel16off;cw;NONE;JBE; Jump if below or equal (CF = 1 or ZF = 1).
0F-86;rel32off;cd;NONE;JBE; Jump if below or equal (CF = 1 or ZF = 1).
76;rel8off;cb;NONE;JNA; Jump if not above (CF = 1 or ZF = 1).
0F-86;rel16off;cw;NONE;JNA; Jump if not above (CF = 1 or ZF = 1).
0F-86;rel32off;cd;NONE;JNA; Jump if not above (CF = 1 or ZF = 1).
77;rel8off;cb;NONE;JNBE; Jump if not below or equal (CF = 0 and ZF = 0).
0F-87;rel16off;cw;NONE;JNBE; Jump if not below or equal (CF = 0 and ZF = 0).
0F-87;rel32off;cd;NONE;JNBE; Jump if not below or equal (CF = 0 and ZF = 0).
77;rel8off;cb;NONE;JA; Jump if above (CF = 0 and ZF = 0).
0F-87;rel16off;cw;NONE;JA; Jump if above (CF = 0 and ZF = 0).
0F-87;rel32off;cd;NONE;JA; Jump if above (CF = 0 and ZF = 0).
78;rel8off;cb;NONE;JS; Jump if sign (SF = 1).
0F-88;rel16off;cw;NONE;JS; Jump if sign (SF = 1).
0F-88;rel32off;cd;NONE;JS; Jump if sign (SF = 1).
79;rel8off;cb;NONE;JNS; Jump if not sign (SF = 0).
0F-89;rel16off;cw;NONE;JNS; Jump if not sign (SF = 0).
0F-89;rel32off;cd;NONE;JNS; Jump if not sign (SF = 0).
7A;rel8off;cb;NONE;JP; Jump if parity (PF = 1).
0F-8A;rel16off;cw;NONE;JP; Jump if parity (PF = 1).
0F-8A;rel32off;cd;NONE;JP; Jump if parity (PF = 1).
7A;rel8off;cb;NONE;JPE; Jump if parity even (PF = 1).
0F-8A;rel16off;cw;NONE;JPE; Jump if parity even (PF = 1).
0F-8A;rel32off;cd;NONE;JPE; Jump if parity even (PF = 1).
7B;rel8off;cb;NONE;JNP; Jump if not parity (PF = 0).
0F-8B;rel16off;cw;NONE;JNP; Jump if not parity (PF = 0).
0F-8B;rel32off;cd;NONE;JNP; Jump if not parity (PF = 0).
7B;rel8off;cb;NONE;JPO; Jump if parity odd (PF = 0).
0F-8B;rel16off;cw;NONE;JPO; Jump if parity odd (PF = 0).
0F-8B;rel32off;cd;NONE;JPO; Jump if parity odd (PF = 0).
7C;rel8off;cb;NONE;JL; Jump if less (SF <> OF).
0F-8C;rel16off;cw;NONE;JL; Jump if less (SF <> OF).
0F-8C;rel32off;cd;NONE;JL; Jump if less (SF <> OF).
7C;rel8off;cb;NONE;JNGE; Jump if not greater or equal (SF <> OF).
0F-8C;rel16off;cw;NONE;JNGE; Jump if not greater or equal (SF <> OF).
0F-8C;rel32off;cd;NONE;JNGE; Jump if not greater or equal (SF <> OF).
7D;rel8off;cb;NONE;JNL; Jump if not less (SF = OF).
0F-8D;rel16off;cw;NONE;JNL; Jump if not less (SF = OF).
0F-8D;rel32off;cd;NONE;JNL; Jump if not less (SF = OF).
7D;rel8off;cb;NONE;JGE; Jump if greater or equal (SF = OF).
0F-8D;rel16off;cw;NONE;JGE; Jump if greater or equal (SF = OF).
0F-8D;rel32off;cd;NONE;JGE; Jump if greater or equal (SF = OF).
7E;rel8off;cb;NONE;JLE; Jump if less or equal (ZF = 1 or SF <> OF).
0F-8E;rel16off;cw;NONE;JLE; Jump if less or equal (ZF = 1 or SF <> OF).
0F-8E;rel32off;cd;NONE;JLE; Jump if less or equal (ZF = 1 or SF <> OF).
7E;rel8off;cb;NONE;JNG; Jump if not greater (ZF = 1 or SF <> OF).
0F-8E;rel16off;cw;NONE;JNG; Jump if not greater (ZF = 1 or SF <> OF).
0F-8E;rel32off;cd;NONE;JNG; Jump if not greater (ZF = 1 or SF <> OF).
7F;rel8off;cb;NONE;JNLE; Jump if not less or equal (ZF = 0 and SF = OF).
0F-8F;rel16off;cw;NONE;JNLE; Jump if not less or equal (ZF = 0 and SF = OF).
0F-8F;rel32off;cd;NONE;JNLE; Jump if not less or equal (ZF = 0 and SF = OF).
7F;rel8off;cb;NONE;JG; Jump if greater (ZF = 0 and SF = OF).
0F-8F;rel16off;cw;NONE;JG; Jump if greater (ZF = 0 and SF = OF).
0F-8F;rel32off;cd;NONE;JG; Jump if greater (ZF = 0 and SF = OF).
E3;rel8off;cb;NONE;JCXZ; Jump short if the 16-bit count register (CX) is zero.
E3;rel8off;cb;NONE;JECXZ; Jump short if the 32-bit count register (ECX) is zero.
E3;rel8off;cb;NONE;JRCXZ; Jump short if the 64-bit count register (RCX) is zero.
EB;rel8off;cb;NONE;JMP_Near_Short; Short jump with the target specified by an 8-bit signed displacement
E9;rel16off;cw;NONE;JMP_Near; Near jump with the target specified by a 16-bit signed displacement
E9;rel32off;cd;NONE;JMP_Near; Near jump with the target specified by a 32-bit signed displacement
FF;reg/mem16;/4;NONE;JMP_Near; Near jump with the target specified reg/mem16.
FF;reg/mem32;/4;NONE;JMP_Near; Near jump with the target specified reg/mem32.(No prefix for encoding in 64-bit mode.)
FF;reg/mem64;/4;NONE;JMP_Near; Near jump with the target specified reg/mem64.
EA;pntr16:16;cd;NONE;JMP_Far; Far jump direct, with the target specified by a far pointer contained in the instruction. (Invalid in 64-bit mode.)
EA;pntr16:32;cp;NONE;JMP_Far; Far jump direct, with the target specified by a far pointer contained in the instruction. (Invalid in 64-bit mode.)
FF;mem16:16;/5;NONE;JMP_Far; Far jump indirect, with the target specified by a far pointer in memory (16-bit operand size).
FF;mem16:32;/5;NONE;JMP_Far; Far jump indirect, with the target specified by a far pointer in memory (32- and 64-bit operand size).
9F;NONE;NONE;NONE;LAHF; Load the SF, ZF, AF, PF, and CF flags into the AH register.
C5;reg16, mem16:16;/r;NONE;LDS; Load DS:reg16 with a far pointer from memory. [Redefined as VEX (2-byte prefix) in 64-bit mode.]
C5;reg32, mem16:32;/r;NONE;LDS; Load DS:reg32 with a far pointer from memory. [Redefined as VEX (2-byte prefix) in 64-bit mode.]
C4;reg16, mem16:16;/r;NONE;LES; Load ES:reg16 with a far pointer from memory. [Redefined as VEX (3-byte prefix) in 64-bit mode.]
C4;reg32, mem16:32;/r;NONE;LES; Load ES:reg32 with a far pointer from memory. [Redefined as VEX (3-byte prefix) in 64-bit mode.]
0F-B4;reg16, mem16:16;/r;NONE;LFS;Load FS:reg16 with a 32-bit far pointer from memory.
0F-B4;reg32, mem16:32;/r;NONE;LFS;Load FS:reg32 with a 48-bit far pointer from memory.
0F-B5;reg16, mem16:16;/r;NONE;LGS;Load GS:reg16 with a 32-bit far pointer from memory.
0F-B5;reg32, mem16:32;/r;NONE;LGS;Load GS:reg32 with a 48-bit far pointer from memory.
0F-B2;reg16, mem16:16;/r;NONE;LSS;Load SS:reg16 with a 32-bit far pointer from memory.
0F-B2;reg32, mem16:32;/r;NONE;LSS; Load SS:reg32 with a 48-bit far pointer from memory.
8D;reg16, mem;/r;NONE;LEA; Store effective address in a 16-bit register.
8D;reg32, mem;/r;NONE;LEA; Store effective address in a 32-bit register.
8D;reg64, mem;/r;NONE;LEA; Store effective address in a 64-bit register.
C9;NONE;NONE;NONE;LEAVE; Set the stack pointer register SP to the value in the BP register and pop BP.Delete Procedure Stack Frame
C9;NONE;NONE;NONE;LEAVE; Set the stack pointer register ESP to the value in the EBP register and pop EBP.(No prefix for encoding this in 64-bit mode.)Delete Procedure Stack Frame
C9;NONE;NONE;NONE;LEAVE; Set the stack pointer register RSP to the value in the RBP register and pop RBP.Delete Procedure Stack Frame
0F-AE-E8;NONE;NONE;NONE;LFENCE; Force strong ordering of (serialize) load operations.
8F-RXB.09-0.1111.0.00-12;reg32;/0;NONE;LLWPCB; Load Lightweight Profiling Control Block Address ModRM.reg augments the opcode and is assigned the value 0. ModRM.r/m (augmented by XOP.R) specifies the register containing the effective address of the LWPCB. ModRM.mod is 11b.
8F-RXB.09-1.1111.0.00-12;reg64;/0;NONE;LLWPCB; Load Lightweight Profiling Control Block Address ModRM.reg augments the opcode and is assigned the value 0. ModRM.r/m (augmented by XOP.R) specifies the register containing the effective address of the LWPCB. ModRM.mod is 11b.
AC;mem8;NONE;NONE;LODS; Load byte at DS:rSI into AL and then increment or decrement rSI.
AD;mem16;NONE;NONE;LODS; Load word at DS:rSI into AX and then increment or decrement rSI.
AD;mem32;NONE;NONE;LODS; Load doubleword at DS:rSI into EAX and then increment or decrement rSI.
AD;mem64;NONE;NONE;LODS; Load quadword at DS:rSI into RAX and then increment or decrement rSI.
AC;NONE;NONE;NONE;LODSB; Load byte at DS:rSI into AL and then increment or decrement rSI.
AD;NONE;NONE;NONE;LODSW; Load the word at DS:rSI into AX and then increment or decrement rSI.
AD;NONE;NONE;NONE;LODSD; Load doubleword at DS:rSI into EAX and then increment or decrement rSI.
AD;NONE;NONE;NONE;LODSQ; Load quadword at DS:rSI into RAX and then increment or decrement rSI.
E2;rel8off;cb;NONE;LOOP; Decrement rCX, then jump short if rCX is not 0.
E1;rel8off;cb;NONE;LOOPE; Decrement rCX, then jump short if rCX is not 0 and ZF is 1
E0;rel8off;cb;NONE;LOOPNE; Decrement rCX, then Jump short if rCX is not 0 and ZF is 0
E0;rel8off;cb;NONE;LOOPNZ; Decrement rCX, then Jump short if rCX is not 0 and ZF is 0
E1;rel8off;cb;NONE;LOOPZ; Decrement rCX, then Jump short if rCX is not 0 and ZF is 1
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Re: Estructuras Binarias x86-64
« Respuesta #3 en: 22 Julio 2020, 22:35 »

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8F-RXB.0A-0.src1.0.00-12;reg32.vvvv, reg/mem32, imm32;/0-id;CF=M;LWPINS;  Lightweight Profiling Insert Record ModRM.reg augments the opcode and is assigned the value 0. The {mod, r/m} field of the ModRM byte (augmented by XOP.R) encodes the second operand. A 4-byte immediate field follows ModRM.
8F-RXB.0A-1.src1.0.00-12;reg64.vvvv, reg/mem32, imm32;/0-id;CF=M;LWPINS;  Lightweight Profiling Insert Record ModRM.reg augments the opcode and is assigned the value 0. The {mod, r/m} field of the ModRM byte (augmented by XOP.R) encodes the second operand. A 4-byte immediate field follows ModRM.
8F-RXB.0A-0.src1.0.00-12;reg32.vvvv, reg/mem32, imm32;/1-id;NONE;LWPVAL; Lightweight Profiling Insert Value ModRM.reg augments the opcode and is assigned the value 001b. The {mod, r/m} field of the ModRM byte (augmented by XOP.R) encodes the second operand. A four-byte immediate field follows ModRM.
8F-RXB.0A-1.src1.0.00-12;reg64.vvvv, reg/mem32, imm32;/1-id;NONE;LWPVAL; Lightweight Profiling Insert Value ModRM.reg augments the opcode and is assigned the value 001b. The {mod, r/m} field of the ModRM byte (augmented by XOP.R) encodes the second operand. A four-byte immediate field follows ModRM.
F3-0F-BD;reg16, reg/mem16;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;LZCNT; Count the number of leading zeros in reg/mem16.
F3-0F-BD;reg32, reg/mem32;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;LZCNT; Count the number of leading zeros in reg/mem32.
F3-0F-BD;reg64, reg/mem64;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;LZCNT; Count the number of leading zeros in reg/mem64.
F3-0F-01-FA;NONE;NONE;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;MCOMMIT; Commit stores to memory
0F-AE-F0;NONE;NONE;NONE;MFENCE; Force strong ordering of (serialized) load and store
0F-01-FA;NONE;NONE;NONE;MONITORX; Establishes a range to be monitored
88;reg/mem8, reg8;/r;NONE;MOV; Move the contents of an 8-bit register to an 8-bit destination register or memory operand.
89;reg/mem16, reg16;/r;NONE;MOV; Move the contents of a 16-bit register to a 16-bit destination register or memory operand.
89;reg/mem32, reg32;/r;NONE;MOV; Move the contents of a 32-bit register to a 32-bit destination register or memory operand.
89;reg/mem64, reg64;/r;NONE;MOV; Move the contents of a 64-bit register to a 64-bit destination register or memory operand.
8A;reg8, reg/mem8;/r;NONE;MOV; Move the contents of an 8-bit register or memory operand to an 8-bit destination register.
8B;reg16, reg/mem16;/r;NONE;MOV; Move the contents of a 16-bit register or memory operand to a 16-bit destination register.
8B;reg32, reg/mem32;/r;NONE;MOV; Move the contents of a 32-bit register or memory operand to a 32-bit destination register.
8B;reg64, reg/mem64;/r;NONE;MOV; Move the contents of a 64-bit register or memory operand to a 64-bit destination register.
8C;reg16/32/64/mem16, segReg;/r;NONE;MOV; Move the contents of a segment register to a 16-bit, 32- bit, or 64-bit destination register or to a 16-bit memory operand.
8E;segReg, reg/mem16;/r;NONE;MOV; Move the contents of a 16-bit register or memory operand to a segment register.
A0;AL, moffset8;NONE;NONE;MOV; Move 8-bit data at a specified memory offset to the AL register
A1;AX, moffset16;NONE;NONE;MOV; Move 16-bit data at a specified memory offset to the AX register
A1;EAX, moffset32;NONE;NONE;MOV; Move 32-bit data at a specified memory offset to the EAX register
A1;RAX, moffset64;NONE;NONE;MOV; Move 64-bit data at a specified memory offset to the RAX register
A2;moffset8, AL;NONE;NONE;MOV; Move the contents of the AL register to an 8-bit memory offset
A3;moffset16, AX;NONE;NONE;MOV; Move the contents of the AX register to a 16-bit memory offset
A3;moffset32, EAX;NONE;NONE;MOV; Move the contents of the EAX register to a 32-bit memory offset
A3;moffset64, RAX;NONE;NONE;MOV; Move the contents of the RAX register to a 64-bit memory offset
B0;reg8, imm8;+rb-ib;NONE;MOV; Move an 8-bit immediate value into an 8-bit register.
B8;reg16, imm16;+rw-iw;NONE;MOV; Move a 16-bit immediate value into a 16-bit register.
B8;reg32, imm32;+rd-id;NONE;MOV; Move an 32-bit immediate value into a 32-bit register.
B8;reg64, imm64;+rq-iq;NONE;MOV; Move an 64-bit immediate value into a 64-bit register.
C6;reg/mem8, imm8;/0-ib;NONE;MOV; Move an 8-bit immediate value to an 8-bit register or memory operand.
C7;reg/mem16, imm16;/0-iw;NONE;MOV; Move a 16-bit immediate value to a 16-bit register or memory operand.
C7;reg/mem32, imm32;/0-id;NONE;MOV; Move a 32-bit immediate value to a 32-bit register or memory operand.
C7;reg/mem64, imm32;/0-id;NONE;MOV; Move a 32-bit signed immediate value to a 64-bit register or memory operand.
0F-38-F0;reg16, mem16;/r;NONE;MOVBE; Load the low word of a general-purpose register from a 16-bit memory location while swapping the bytes.
0F-38-F0;reg32, mem32;/r;NONE;MOVBE; Load the low doubleword of a general-purpose register from a 32-bit memory location while swapping the bytes.
0F-38-F0;reg64, mem64;/r;NONE;MOVBE; Load a 64-bit register from a 64-bit memory location
0F-38-F1;mem16, reg16;/r;NONE;MOVBE; Store the low word of a general-purpose register to a 16-bit memory location while swapping the bytes.
0F-38-F1;mem32, reg32;/r;NONE;MOVBE; Store the low doubleword of a general-purpose register to a 32-bit memory location while swapping the bytes.
0F-38-F1;mem64, reg64;/r;NONE;MOVBE; Store the contents of a 64-bit general-purpose register to a 64-bit memory location while swapping the bytes.
66-0F-6E;xmm, reg/mem32;/r;NONE;MOVD; Move 32-bit value from a general-purpose register or 32-bit memory location to an XMM register.
66-0F-6E;xmm, reg/mem64;/r;NONE;MOVD1; Move 64-bit value from a general-purpose register or 64-bit memory location to an XMM register.
66-0F-7E;reg/mem32, xmm;/r;NONE;MOVD; Move 32-bit value from an XMM register to a 32-bit general-purpose register or memory location.
66-0F-7E;reg/mem64, xmm;/r;NONE;MOVD1; Move 64-bit value from an XMM register to a 64-bit general-purpose register or memory location.
0F-6E;mmx, reg/mem32;/r;NONE;MOVD; Move 32-bit value from a general-purpose register or 32-bit memory location to an MMX register.
0F-6E;mmx, reg/mem64;/r;NONE;MOVD; Move 64-bit value from a general-purpose register or 64-bit memory location to an MMX register.
0F-7E;reg/mem32, mmx;/r;NONE;MOVD; Move 32-bit value from an MMX register to a 32-bit general-purpose register or memory location.
0F-7E;reg/mem64, mmx;/r;NONE;MOVD; Move 64-bit value from an MMX register to a 64-bit general-purpose register or memory location.
66-0F-50;reg32, xmm;/r;NONE;MOVMSKPD; Move sign bits 127 and 63 in an XMM register to a 32-bit
0F-50;reg32, xmm;/r;NONE;MOVMSKPS; Move sign bits 127, 95, 63, 31 in an XMM register to a 32-bit general-purpose register.
0F-C3;mem32, reg32;/r;NONE;MOVNTI; Stores a 32-bit general-purpose register value into a 32- bit memory location, minimizing cache pollution.
0F-C3;mem64, reg64;/r;NONE;MOVNTI; Stores a 64-bit general-purpose register value into a 64- bit memory location, minimizing cache pollution.
A4;mem8, mem8;NONE;NONE;MOVS; Move byte at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;mem16, mem16;NONE;NONE;MOVS; Move word at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;mem32, mem32;NONE;NONE;MOVS; Move doubleword at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;mem64, mem64;NONE;NONE;MOVS; Move quadword at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A4;NONE;NONE;NONE;MOVSB; Move byte at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;NONE;NONE;NONE;MOVSW; Move word at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;NONE;NONE;NONE;MOVSD; Move doubleword at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
A5;NONE;NONE;NONE;MOVSQ; Move quadword at DS:rSI to ES:rDI, and then increment or decrement rSI and rDI.
0F-BE;reg16, reg/mem8;/r;NONE;MOVSX; Move the contents of an 8-bit register or memory location to a 16-bit register with sign extension.
0F-BE;reg32, reg/mem8;/r;NONE;MOVSX; Move the contents of an 8-bit register or memory location to a 32-bit register with sign extension.
0F-BE;reg64, reg/mem8;/r;NONE;MOVSX; Move the contents of an 8-bit register or memory location to a 64-bit register with sign extension.
0F-BF;reg32, reg/mem16;/r;NONE;MOVSX; Move the contents of an 16-bit register or memory location to a 32-bit register with sign extension.
0F-BF;reg64, reg/mem16;/r;NONE;MOVSX; Move the contents of an 16-bit register or memory location to a 64-bit register with sign extension.
63;reg64, reg/mem32;/r;NONE;MOVSXD; Move the contents of a 32-bit register or memory operand to a 64-bit register with sign extension.
0F-B6;reg16, reg/mem8;/r;NONE;MOVZX; Move the contents of an 8-bit register or memory operand to a 16-bit register with zero-extension.
0F-B6;reg32, reg/mem8;/r;NONE;MOVZX; Move the contents of an 8-bit register or memory operand to a 32-bit register with zero-extension.
0F-B6;reg64, reg/mem8;/r;NONE;MOVZX; Move the contents of an 8-bit register or memory operand to a 64-bit register with zero-extension.
0F-B7;reg32, reg/mem16;/r;NONE;MOVZX; Move the contents of a 16-bit register or memory operand to a 32-bit register with zero-extension.
0F-B7;reg64, reg/mem16;/r;NONE;MOVZX; Move the contents of a 16-bit register or memory operand to a 64-bit register with zero-extension.
F6;reg/mem8;/4;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;MUL; Multiplies an 8-bit register or memory operand by the contents of the AL register and stores the result in the AX register.
F7;reg/mem16;/4;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;MUL; Multiplies a 16-bit register or memory operand by the contents of the AX register and stores the result in the DX:AX register.
F7;reg/mem32;/4;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;MUL; Multiplies a 32-bit register or memory operand by the contents of the EAX register and stores the result in the EDX:EAX register.
F7;reg/mem64;/4;OF=M-SF=U-ZF=U-AF=U-PF=U-CF=M;MUL; Multiplies a 64-bit register or memory operand by the contents of the RAX register and stores the result in the RDX:RAX register.
C4-RXB.02-0.dest2.0.11-F6;reg32, reg32, reg/mem32;/r;NONE;MULX; Multiply Unsigned
C4-RXB.02-1.dest2.0.11-F6;reg64, reg64, reg/mem64;/r;NONE;MULX; Multiply Unsigned
0F-01-FB;NONE;NONE;NONE;MWAITX; an implementation-dependent optimized state until occurrence of a class of events Causes the processor to stop instruction execution and enter
F6;reg/mem8;/3;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;NEG; Performs a two’s complement negation on an 8-bit register or memory operand.
F7;reg/mem16;/3;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;NEG; Performs a two’s complement negation on a 16-bit register or memory operand.
F7;reg/mem32;/3;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;NEG; Performs a two’s complement negation on a 32-bit register or memory operand.
F7;reg/mem64;/3;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;NEG; Performs a two’s complement negation on a 64-bit register or memory operand.
90;NONE;NONE;NONE;NOP; Performs no operation.
0F-1F;reg/mem16;/0;NONE;NOP; Performs no operation on a 16-bit register or memory operand
0F-1F;reg/mem32;/0;NONE;NOP; Performs no operation on a 32-bit register or memory operand
0F-1F;reg/mem64;/0;NONE;NOP; Performs no operation on a 64-bit register or memory operand
F6;reg/mem8;/2;NONE;NOT; Complements the bits in an 8-bit register or memory operand
F7;reg/mem16;/2;NONE;NOT; Complements the bits in a 16-bit register or memory operand
F7;reg/mem32;/2;NONE;NOT; Complements the bits in a 32-bit register or memory operand
F7;reg/mem64;/2;NONE;NOT; Compliments the bits in a 64-bit register or memory operand
0C;AL, imm8;ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR;or the contents of AL with an immediate 8-bit value.Logical OR
0D;AX, imm16;iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR;or the contents of AX with an immediate 16-bit value.Logical OR
0D;EAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR;or the contents of EAX with an immediate 32-bit value.Logical OR
0D;RAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR;or the contents of RAX with a sign-extended immediate 32-bit value.Logical OR
80;reg/mem8, imm8;/1-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of an 8-bit register or memory operand and an immediate 8-bit value.
81;reg/mem16, imm16;/1-iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 16-bit register or memory operand and an immediate 16-bit value.
81;reg/mem32, imm32;/1-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 32-bit register or memory operand and an immediate 32-bit value.
81;reg/mem64, imm32;/1-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 64-bit register or memory operand and sign-extended immediate 32-bit value.
83;reg/mem16, imm8;/1-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 16-bit register or memory operand and a sign-extended immediate 8-bit value.
83;reg/mem32, imm8;/1-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 32-bit register or memory operand and a sign-extended immediate 8-bit value.
83;reg/mem64, imm8;/1-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 64-bit register or memory operand and a sign-extended immediate 8-bit value.
08;reg/mem8, reg8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of an 8-bit register or memory operand with the contents of an 8-bit register.
09;reg/mem16, reg16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 16-bit register or memory operand with the contents of a 16-bit register.
09;reg/mem32, reg32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 32-bit register or memory operand with the contents of a 32-bit register.
09;reg/mem64, reg64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 64-bit register or memory operand with the contents of a 64-bit register.
0A;reg8, reg/mem8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of an 8-bit register with the contentsof an 8-bit register or memory operand.
0B;reg16, reg/mem16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 16-bit register with the contentsof a 16-bit register or memory operand.
0B;reg32, reg/mem32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 32-bit register with the contentsof a 32-bit register or memory operand.
0B;reg64, reg/mem64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;OR; or the contents of a 64-bit register with the contentsof a 64-bit register or memory operand.
E6;imm8, AL;ib;NONE;OUT; Output the byte in the AL register to the port specified by an 8-bit immediate value.
E7;imm8, AX;ib;NONE;OUT; Output the word in the AX register to the port specified by an 8-bit immediate value.
E7;imm8, EAX;ib;NONE;OUT; Output the doubleword in the EAX register to the port specified by an 8-bit immediate value.
EE;DX, AL;NONE;NONE;OUT; Output byte in AL to the output port specified in DX.
EF;DX, AX;NONE;NONE;OUT; Output word in AX to the output port specified in DX.
EF;DX, EAX;NONE;NONE;OUT; Output doubleword in EAX to the output port specified in DX.
6E;DX, mem8;NONE;NONE;OUTS; Output the byte in DS:rSI to the port specified in DX, then increment or decrement rSI.
6F;DX, mem16;NONE;NONE;OUTS; Output the word in DS:rSI to the port specified in DX, then increment or decrement rSI.
6F;DX, mem32;NONE;NONE;OUTS; Output the doubleword in DS:rSI to the port specified in DX, then increment or decrement rSI.
6E;NONE;NONE;NONE;OUTSB; Output the byte in DS:rSI to the port specified in DX, then increment or decrement rSI.
6F;NONE;NONE;NONE;OUTSW; Output the word in DS:rSI to the port specified in DX, then increment or decrement rSI.
6F;NONE;NONE;NONE;OUTSD; Output the doubleword in DS:rSI to the port specified in DX, then increment or decrement rSI.
F3-90;NONE;NONE;NONE;PAUSE; Provides a hint to processor that a spin loop is being executed.
C4-RXB.02-0.src.0.11-F5;reg32, reg32, reg/mem32;/r;NONE;PDEP; Parallel Deposit Bits dest mask
C4-RXB.02-1.src.0.11-F5;reg64, reg64, reg/mem64;/r;NONE;PDEP; Parallel Deposit Bits dest mask
C4-RXB.02-0.src.0.10-F5;reg32, reg32, reg/mem32;/r;NONE;PEXT; Parallel Extract Bits mask src
C4-RXB.02-1.src.0.10-F5;reg64, reg64, reg/mem64;/r;NONE;PEXT; Parallel Extract Bits mask src
8F;reg/mem16;/0;NONE;POP; Pop the top of the stack into a 16-bit register or memory location.
8F;reg/mem32;/0;NONE;POP; Pop the top of the stack into a 32-bit register or memory location. (No prefix for encoding this in 64-bit mode.)
8F;reg/mem64;/0;NONE;POP; Pop the top of the stack into a 64-bit register or memory location.
58;reg16;+rw;NONE;POP; Pop the top of the stack into a 16-bit register.
58;reg32;+rd;NONE;POP; Pop the top of the stack into a 32-bit register. (No prefix for encoding this in 64-bit mode.)
58;reg64;+rq;NONE;POP; Pop the top of the stack into a 64-bit register.
1F;DS;NONE;NONE;POP; Pop the top of the stack into the DS register. (Invalid in 64-bit mode.)
07;ES;NONE;NONE;POP; Pop the top of the stack into the ES register. (Invalid in 64-bit mode.)
17;SS;NONE;NONE;POP; Pop the top of the stack into the SS register. (Invalid in 64-bit mode.)
0F-A1;FS;NONE;NONE;POP; Pop the top of the stack into the FS register.
0F-A9;GS;NONE;NONE;POP; Pop the top of the stack into the GS register.
61;NONE;NONE;NONE;POPA; Pop the DI, SI, BP, SP, BX, DX, CX, and AX registers. (Invalid in 64-bit mode.)
61;NONE;NONE;NONE;POPAD; Pop the EDI, ESI, EBP, ESP, EBX, EDX, ECX, and EAX registers. (Invalid in 64-bit mode.)
F3-0F-B8;reg16, reg/mem16;/r;OF=0-SF=0-ZF=M-AF=0-PF=0-CF=0;POPCNT; Count the 1s in reg/mem16.
F3-0F-B8;reg32, reg/mem32;/r;OF=0-SF=0-ZF=M-AF=0-PF=0-CF=0;POPCNT; Count the 1s in reg/mem32.
F3-0F-B8;reg64, reg/mem64;/r;OF=0-SF=0-ZF=M-AF=0-PF=0-CF=0;POPCNT; Count the 1s in reg/mem64.
9D;NONE;NONE;ID=M-VIF=M-AC=M-RF=0-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;POPF; Pop a word from the stack into the FLAGS register.
9D;NONE;NONE;ID=M-VIF=M-AC=M-RF=0-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;POPFD; Pop a double word from the stack into the EFLAGS register. (No prefix for encoding this in 64-bit mode.)
9D;NONE;NONE;ID=M-VIF=M-AC=M-RF=0-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;POPFQ; Pop a quadword from the stack to the RFLAGS register.
0F-0D;mem8;/0;NONE;PREFETCH; Prefetch processor cache line into L1 data cache.
0F-0D;mem8;/1;NONE;PREFETCHW; Prefetch processor cache line into L1 data cache and
0F-18;mem8;/0;NONE;PREFETCH_NTA; Move data closer to the processor using the NTA Non-Temporal Access—Move the specified data into the processor with minimum cache pollution. This is intended for data that will be used only once, rather than repeatedly. The specific technique for minimizing cache pollution is implementation-dependent and may include such techniques as allocating space in a software-invisible buffer, allocating a cache line in only a single way, etc. For details, see the software-optimization documentation for a particular hardware implementation.
0F-18;mem8;/1;NONE;PREFETCH_T0; Move data closer to the processor using the T0 All Cache Levels—Move the specified data into all cache levels.
0F-18;mem8;/2;NONE;PREFETCH_T1; Move data closer to the processor using the T1 Level 2 and Higher—Move the specified data into all cache levels except 0th level (L1) cache.
0F-18;mem8;/3;NONE;PREFETCH_T2; Move data closer to the processor using the T2 Level 3 and Higher—Move the specified data into all cache levels except 0th level (L1) and 1st level (L2) caches.
FF;reg/mem16;/6;NONE;PUSH; Push the contents of a 16-bit register or memory operand onto the stack.
FF;reg/mem32;/6;NONE;PUSH; Push the contents of a 32-bit register or memory operand onto the stack. (No prefix for encoding this in 64-bit mode.)
FF;reg/mem64;/6;NONE;PUSH; Push the contents of a 64-bit register or memory operand onto the stack.
50;reg16;+rw;NONE;PUSH; Push the contents of a 16-bit register onto the stack.
50;reg32;+rd;NONE;PUSH; Push the contents of a 32-bit register onto the stack. (No prefix for encoding this in 64-bit mode.)
50;reg64;+rq;NONE;PUSH; Push the contents of a 64-bit register onto the stack.
6A;imm8;ib;NONE;PUSH; Push an 8-bit immediate value (sign-extended to 16, 32, or 64 bits) onto the stack.
68;imm16;iw;NONE;PUSH; Push a 16-bit immediate value onto the stack.
68;imm32;id;NONE;PUSH; Push a 32-bit immediate value onto the stack. (No prefix for encoding this in 64-bit mode.)
68;imm64;id;NONE;PUSH; Push a sign-extended 32-bit immediate value onto the
0E;CS;NONE;NONE;PUSH; Push the CS selector onto the stack. (Invalid in 64-bit mode.)
16;SS;NONE;NONE;PUSH; Push the SS selector onto the stack. (Invalid in 64-bit mode.)
1E;DS;NONE;NONE;PUSH; Push the DS selector onto the stack.  (Invalid in 64-bit mode.)
06;ES;NONE;NONE;PUSH; Push the ES selector onto the stack. (Invalid in 64-bit mode.)
0F-A0;FS;NONE;NONE;PUSH; Push the FS selector onto the stack.
0F-A8;GS;NONE;NONE;PUSH; Push the GS selector onto the  stack.
60;NONE;NONE;NONE;PUSHA; Push the contents of the AX, CX, DX, BX, original SP,BP, SI, and DI registers onto the stack. (Invalid in 64-bit mode.)
60;NONE;NONE;NONE;PUSHAD; Push the contents of the EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI registers onto the stack. (Invalid in 64-bit mode.)
9C;NONE;NONE;NONE;PUSHF; Push the FLAGS word onto the stack.
9C;NONE;NONE;NONE;PUSHFD; Push the EFLAGS doubleword onto stack. (No prefix encoding this in 64-bit mode.)
9C;NONE;NONE;NONE;PUSHFQ; Push the RFLAGS quadword onto stack.
D0;reg/mem8,1;/2;OF=M-CF=M;RCL; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location left 1 bit.
D2;reg/mem8, CL;/2;OF=M-CF=M;RCL; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location left the number of bits specified in the CL register.
C0;reg/mem8, imm8;/2-ib;OF=M-CF=M;RCL; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/2;OF=M-CF=M;RCL; Rotate the 17 bits consisting of the carry flag and a 16- bit register or memory location left 1 bit.
D3;reg/mem16, CL;/2;OF=M-CF=M;RCL; Rotate the 17 bits consisting of the carry flag and a 16- bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem16, imm8;/2-ib;OF=M-CF=M;RCL; Rotate the 17 bits consisting of the carry flag and a 16- bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/2;OF=M-CF=M;RCL; Rotate the 33 bits consisting of the carry flag and a 32- bit register or memory location left 1 bit.
D3;reg/mem32, CL;/2;OF=M-CF=M;RCL; Rotate 33 bits consisting of the carry flag and a 32-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem32, imm8;/2-ib;OF=M-CF=M;RCL; Rotate the 33 bits consisting of the carry flag and a 32- bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/2;OF=M-CF=M;RCL; Rotate the 65 bits consisting of the carry flag and a 64- bit register or memory location left 1 bit.
D3;reg/mem64, CL;/2;OF=M-CF=M;RCL; Rotate the 65 bits consisting of the carry flag and a 64-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem64, imm8;/2-ib;OF=M-CF=M;RCL; Rotates the 65 bits consisting of the carry flag and a 64- bit register or memory location left the number of bits specified by an 8-bit immediate value.
D0;reg/mem8, 1;/3;OF=M-CF=M;RCR; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location right 1 bit.
D2;reg/mem8,CL;/3;OF=M-CF=M;RCR; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location right the number of bits specified in the CL register.
C0;reg/mem8,imm8;/3-ib;OF=M-CF=M;RCR; Rotate the 9 bits consisting of the carry flag and an 8-bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem16,1;/3;OF=M-CF=M;RCR; Rotate the 17 bits consisting of the carry flag and a 16- bit register or memory location right 1 bit.
D3;reg/mem16,CL;/3;OF=M-CF=M;RCR; Rotate the17 bits consisting of the carry flag and a 16-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem16, imm8;/3-ib;OF=M-CF=M;RCR; Rotate the 17 bits consisting of the carry flag and a 16- bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem32,1;/3;OF=M-CF=M;RCR; Rotate the 33 bits consisting of the carry flag and a 32- bit register or memory location right 1 bit.
D3;reg/mem32,CL;/3;OF=M-CF=M;RCR; Rotate 33 bits consisting of the carry flag and a 32-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem32, imm8;/3-ib;OF=M-CF=M;RCR; Rotate the 33 bits consisting of the carry flag and a 32- bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem64,1;/3;OF=M-CF=M;RCR; Rotate the 65 bits consisting of the carry flag and a 64- bit register or memory location right 1 bit.
D3;reg/mem64,CL;/3;OF=M-CF=M;RCR; Rotate 65 bits consisting of the carry flag and a 64-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem64, imm8;/3-ib;OF=M-CF=M;RCR; Rotate the 65 bits consisting of the carry flag and a 64- bit register or memory location right the number of bits specified by an 8-bit immediate value.
F3-0F-AE;reg32;/0;NONE;RDFSBASE; Copy the lower 32 bits of FS.base to the specified general-purpose register.
F3-0F-AE;reg64;/0;NONE;RDFSBASE; Copy the entire 64-bit contents of FS.base to the specified general-purpose register.
F3-0F-AE;reg32;/1;NONE;RDGSBASE; Copy the lower 32 bits of GS.base to the specified general-purpose register.
F3-0F-AE;reg64;/1;NONE;RDGSBASE; Copy the entire 64-bit contents of GS.base to the specified general-purpose register.
F3-0F-C7;NONE;/7;NONE;RDPID; Read TSC_AUX
0F-01-FD;NONE;NONE;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDPRU; Copy register specified by ECX into EDX:EAX
0F-C7;reg16;/6;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDRAND; Load the destination register with a 16-bit random
0F-C7;reg32;/6;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDRAND; Load the destination register with a 32-bit random
0F-C7;reg64;/6;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDRAND; Load the destination register with a 64-bit random
0F-C7;reg16;/7;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDSEED; Read 16-bit random seed
0F-C7;reg32;/7;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDSEED; Read 32-bit random seed
0F-C7;reg64;/7;OF=0-SF=0-ZF=0-AF=0-PF=0-CF=M;RDSEED; Read 64-bit random seed
C3;NONE;NONE;NONE;RET_near; Near return to the calling procedure.
C2;imm16;iw;NONE;RET_near; Near return to the calling procedure then pop the specified number of bytes from the stack.
CB;NONE;NONE;NONE;RET_Far; Far return to the calling procedure.
CA;imm16;iw;NONE;RET_Far; Far return to the calling procedure, then pop the specified number of bytes from the stack.
D0;reg/mem8, 1;/0;OF=M-CF=M;ROL; Rotate an 8-bit register or memory operand left 1 bit.
D2;reg/mem8, CL;/0;OF=M-CF=M;ROL; Rotate an 8-bit register or memory operand left the number of bits specified in the CL register.
C0;reg/mem8, imm8;/0-ib;OF=M-CF=M;ROL; Rotate an 8-bit register or memory operand left the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/0;OF=M-CF=M;ROL; Rotate a 16-bit register or memory operand left 1 bit.
D3;reg/mem16, CL;/0;OF=M-CF=M;ROL; Rotate a 16-bit register or memory operand left the number of bits specified in the CL register.
C1;reg/mem16, imm8;/0-ib;OF=M-CF=M;ROL; Rotate a 16-bit register or memory operand left the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/0;OF=M-CF=M;ROL; Rotate a 32-bit register or memory operand left 1 bit.
D3;reg/mem32, CL;/0;OF=M-CF=M;ROL; Rotate a 32-bit register or memory operand left the number of bits specified in the CL register.
C1;reg/mem32, imm8;/0-ib;OF=M-CF=M;ROL; Rotate a 32-bit register or memory operand left the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/0;OF=M-CF=M;ROL; Rotate a 64-bit register or memory operand left 1 bit.
D3;reg/mem64, CL;/0;OF=M-CF=M;ROL; Rotate a 64-bit register or memory operand left the number of bits specified in the CL register.
C1;reg/mem64, imm8;/0-ib;OF=M-CF=M;ROL; Rotate a 64-bit register or memory operand left the number of bits specified by an 8-bit immediate value.
D0;reg/mem8, 1;/1;OF=M-CF=M;ROR; Rotate an 8-bit register or memory location right 1 bit.
D2;reg/mem8, CL;/1;OF=M-CF=M;ROR; Rotate an 8-bit register or memory location right the number of bits specified in the CL register.
C0;reg/mem8, imm8;/1-ib;OF=M-CF=M;ROR; Rotate an 8-bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/1;OF=M-CF=M;ROR; Rotate a 16-bit register or memory location right 1 bit.
D3;reg/mem16, CL;/1;OF=M-CF=M;ROR; Rotate a 16-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem16, imm8;/1-ib;OF=M-CF=M;ROR; Rotate a 16-bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/1;OF=M-CF=M;ROR; Rotate a 32-bit register or memory location right 1 bit.
D3;reg/mem32, CL;/1;OF=M-CF=M;ROR; Rotate a 32-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem32, imm8;/1-ib;OF=M-CF=M;ROR; Rotate a 32-bit register or memory location right the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/1;OF=M-CF=M;ROR; Rotate a 64-bit register or memory location right 1 bit.
D3;reg/mem64, CL;/1;OF=M-CF=M;ROR; Rotate a 64-bit register or memory operand right the number of bits specified in the CL register.
C1;reg/mem64, imm8;/1-ib;OF=M-CF=M;ROR; Rotate a 64-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
C4-RXB.03-0.1111.0.11-F0;reg32, reg/mem32, imm8;/r-ib;NONE;RORX; Rotate Right Extended
C4-RXB.03-1.1111.0.11-F0;reg64, reg/mem64, imm8;/r-ib;NONE;RORX; Rotate Right Extended
9E;NONE;NONE;SF=M-ZF=M-AF=M-PF=M-CF=M;SAHF; Loads the sign flag, the zero flag, the auxiliary flag, the parity flag, and the carry flag from the AH register into the lower 8 bits of the EFLAGS register.
D0;reg/mem8, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift an 8-bit register or memory location left 1 bit.
D2;reg/mem8, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift an 8-bit register or memory location left the number of bits specified in the CL register.
C0;reg/mem8, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift an 8-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 16-bit register or memory location left 1 bit.
D3;reg/mem16, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 16-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem16, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 16-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 32-bit register or memory location left 1 bit.
D3;reg/mem32, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 32-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem32, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 32-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 64-bit register or memory location left 1 bit.
D3;reg/mem64, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 64-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem64, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAL; Shift a 64-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D0;reg/mem8, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift an 8-bit register or memory location by 1 bit.
D2;reg/mem8, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift an 8-bit register or memory location left the number of bits specified in the CL register.
C0;reg/mem8, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift an 8-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 16-bit register or memory location left 1 bit.
D3;reg/mem16, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 16-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem16, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 16-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 32-bit register or memory location left 1 bit.
D3;reg/mem32, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 32-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem32, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 32-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 64-bit register or memory location left 1 bit.
D3;reg/mem64, CL;/4;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 64-bit register or memory location left the number of bits specified in the CL register.
C1;reg/mem64, imm8;/4-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHL; Shift a 64-bit register or memory location left the number of bits specified by an 8-bit immediate value.
D0;reg/mem8, 1;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 8-bit register or memory operand right 1
D2;reg/mem8, CL;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 8-bit register or memory operand right the number of bits specified in the CL register.
C0;reg/mem8, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 8-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 16-bit register or memory operand right 1
D3;reg/mem16, CL;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 16-bit register or memory operand right the number of bits specified in the CL register.
C1;reg/mem16, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 16-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 32-bit register or memory location 1 bit.
D3;reg/mem32, CL;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 32-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem32, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 32-bit register or memory location right the number of bits specified by an 8-bit immediatevalue.
D1;reg/mem64, 1;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 64-bit register or memory location right 1
D3;reg/mem64, CL;/7;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 64-bit register or memory location right the number of bits specified in the CL register.
C1;reg/mem64, imm8;/7-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SAR; Shift a signed 64-bit register or memory location right the number of bits specified by an 8-bit immediate value.
C4-RXB.02-0.src2.0.10-F7;reg32, reg/mem32, reg32;/r;NONE;SARX; Shift Right Arithmetic Extended
C4-RXB.02-1.src2.0.10-F7;reg64, reg/mem64, reg64;/r;NONE;SARX; Shift Right Arithmetic Extended
1D;AX, imm16;iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB;Subtract an immediate 16-bit value from the AX register
1C;AL, imm8;ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract an immediate 8-bit value from the AL register SBB AX, imm16
1D;EAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract an immediate 32-bit value from the EAX register with borrow.
1D;RAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract a sign-extended immediate 32-bit value from the RAX register with borrow.
80;reg/mem8, imm8;/3-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract an immediate 8-bit value from an 8-bit register or memory location with borrow.
81;reg/mem16, imm16;/3-iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract an immediate 16-bit value from a 16-bit register or memory location with borrow.
81;reg/mem32, imm32;/3-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract an immediate 32-bit value from a 32-bit register or memory location with borrow.
81;reg/mem64, imm32;/3-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract a sign-extended immediate 32-bit value from a 64-bit register or memory location with borrow.
83;reg/mem16, imm8;/3-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract a sign-extended 8-bit immediate value from a 16-bit register or memory location with borrow.
83;reg/mem32, imm8;/3-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract a sign-extended 8-bit immediate value from a 32-bit register or memory location with borrow.
83;reg/mem64, imm8;/3-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract a sign-extended 8-bit immediate value from a 64-bit register or memory location with borrow.
18;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of an 8-bit register from an 8-bit register or memory location with borrow.
19;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 16-bit register from a 16-bit register or memory location with borrow.
19;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 32-bit register from a 32-bit register or memory location with borrow.
19;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 64-bit register from a 64-bit register or memory location with borrow.
1A;reg8, reg/mem8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of an 8-bit register or memory location from the contents of an 8-bit register with borrow.
1B;reg16, reg/mem16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 16-bit register or memory location from the contents of a 16-bit register with borrow.
1B;reg32, reg/mem32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 32-bit register or memory location from the contents of a 32-bit register with borrow.
1B;reg64, reg/mem64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SBB; Subtract the contents of a 64-bit register or memory location from the contents of a 64-bit register with borrow.
AE;mem8;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCAS; Compare the contents of the AL register with the byte at ES:rDI, and then increment or decrement rDI.
AF;mem16;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCAS; Compare the contents of the AX register with the word at ES:rDI, and then increment or decrement rDI.
AF;mem32;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCAS; Compare the contents of the EAX register with the doubleword at ES:rDI, and then increment or decrement rDI.
AF;mem64;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCAS; Compare the contents of the RAX register with the quadword at ES:rDI, and then increment or decrement rDI.
AE;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCASB; Compare the contents of the AL register with the byte at ES:rDI, and then increment or decrement rDI.
AF;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCASW; Compare the contents of the AX register with the word at ES:rDI, and then increment or decrement rDI.
AF;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCASD; Compare the contents of the EAX register with the doubleword at ES:rDI, and then increment or decrement rDI.
AF;NONE;NONE;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SCASQ; Compare the contents of the RAX register with the quadword at ES:rDI, and then increment or decrement rDI.
0F-90;reg/mem8;/0;NONE;SETO;Set byte if overflow (OF = 1).
0F-91;reg/mem8;/0;NONE;SETNO;Set byte if not overflow (OF = 0).
0F-92;reg/mem8;/0;NONE;SETB; Set byte if below (CF = 1).
0F-92;reg/mem8;/0;NONE;SETC; Set byte if carry (CF = 1).
0F-92;reg/mem8;/0;NONE;SETNAE; Set byte if not above or equal (CF = 1).
0F-93;reg/mem8;/0;NONE;SETNB; Set byte if not below (CF = 0).
0F-93;reg/mem8;/0;NONE;SETNC; Set byte if not carry (CF = 0).
0F-93;reg/mem8;/0;NONE;SETAE; Set byte if above or equal (CF = 0).
0F-94;reg/mem8;/0;NONE;SETZ; Set byte if zero (ZF = 1).
0F-94;reg/mem8;/0;NONE;SETE; Set byte if equal (ZF = 1).
0F-95;reg/mem8;/0;NONE;SETNZ; Set byte if not zero (ZF = 0).
0F-95;reg/mem8;/0;NONE;SETNE; Set byte if not equal (ZF = 0).
0F-96;reg/mem8;/0;NONE;SETBE; Set byte if below or equal (CF = 1 or ZF = 1).
0F-96;reg/mem8;/0;NONE;SETNA; Set byte if not above (CF = 1 or ZF = 1).
0F-97;reg/mem8;/0;NONE;SETNBE; Set byte if not below or equal (CF = 0 and ZF = 0).
0F-97;reg/mem8;/0;NONE;SETA; Set byte if above (CF = 0 and ZF = 0).
0F-98;reg/mem8;/0;NONE;SETS; Set byte if sign (SF = 1).
0F-99;reg/mem8;/0;NONE;SETNS; Set byte if not sign (SF = 0).
0F-9A;reg/mem8;/0;NONE;SETP; Set byte if parity (PF = 1).
0F-9A;reg/mem8;/0;NONE;SETPE; Set byte if parity even (PF = 1).
0F-9B;reg/mem8;/0;NONE;SETNP; Set byte if not parity (PF = 0).
0F-9B;reg/mem8;/0;NONE;SETPO; Set byte if parity odd (PF = 0).
0F-9C;reg/mem8;/0;NONE;SETL; Set byte if less (SF <> OF).
0F-9C;reg/mem8;/0;NONE;SETNGE; Set byte if not greater or equal (SF <> OF).
0F-9D;reg/mem8;/0;NONE;SETNL; Set byte if not less (SF = OF).
0F-9D;reg/mem8;/0;NONE;SETGE; Set byte if greater or equal (SF = OF).
0F-9E;reg/mem8;/0;NONE;SETLE; Set byte if less or equal (ZF = 1 or SF <> OF).
0F-9E;reg/mem8;/0;NONE;SETNG; Set byte if not greater (ZF = 1 or SF <> OF).
0F-9F;reg/mem8;/0;NONE;SETNLE; Set byte if not less or equal (ZF = 0 and SF = OF).
0F-9F;reg/mem8;/0;NONE;SETG; Set byte if greater (ZF = 0 and SF = OF).
0F-AE-F8;NONE;NONE;NONE;SFENCE; Force strong ordering of (serialized) store operations.
0F-A4;reg/mem16, reg16, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 16-bit destination register or memory operand to the left the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-A5;reg/mem16, reg16, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 16-bit destination register or memory operand to the left the number of bits specified in the CL register, while shifting in bits from the second operand.
0F-A4;reg/mem32, reg32, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 32-bit destination register or memory operand to the left the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-A5;reg/mem32, reg32, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 32-bit destination register or memory operand to the left the number of bits specified in the CL register, while shifting in bits from the second operand.
0F-A4;reg/mem64, reg64, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 64-bit destination register or memory operand to the left the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-A5;reg/mem64, reg64, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHLD; Shift bits of a 64-bit destination register or memory operand to the left the number of bits specified in the CL register, while shifting in bits from the second operand.
C4-RXB.02-0.src2.0.01-F7;reg32, reg/mem32, reg32;/r;NONE;SHLX; Shift Left Logical Extended
C4-RXB.02-1.src2.0.01-F7;reg64, reg/mem64, reg64;/r;NONE;SHLX; Shift Left Logical Extended
D0;reg/mem8, 1;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift an 8-bit register or memory operand right 1 bit.
D2;reg/mem8, CL;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift an 8-bit register or memory operand right the number of bits specified in the CL register.
C0;reg/mem8, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift an 8-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
D1;reg/mem16, 1;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 16-bit register or memory operand right 1 bit.
D3;reg/mem16, CL;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 16-bit register or memory operand right the number of bits specified in the CL register.
C1;reg/mem16, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 16-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
D1;reg/mem32, 1;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 32-bit register or memory operand right 1 bit.
D3;reg/mem32, CL;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 32-bit register or memory operand right the number of bits specified in the CL register.
C1;reg/mem32, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 32-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
D1;reg/mem64, 1;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 64-bit register or memory operand right 1 bit.
D3;reg/mem64, CL;/5;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 64-bit register or memory operand right the number of bits specified in the CL register.
C1;reg/mem64, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHR; Shift a 64-bit register or memory operand right the number of bits specified by an 8-bit immediate value.
0F-AC;reg/mem16, reg16, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 16-bit destination register or memory operand to the right the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-AD;reg/mem16, reg16, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 16-bit destination register or memory operand to the right the number of bits specified in the CL register, while shifting in bits from the second operand.
0F-AC;reg/mem32, reg32, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 32-bit destination register or memory operand to the right the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-AD;reg/mem32, reg32, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 32-bit destination register or memory operand to the right the number of bits specified in the CL register, while shifting in bits from the second operand.
0F-AC;reg/mem64, reg64, imm8;/r-ib;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 64-bit destination register or memory operand to the right the number of bits specified in an 8- bit immediate value, while shifting in bits from the second operand.
0F-AD;reg/mem64, reg64, CL;/r;OF=M-SF=M-ZF=M-AF=U-PF=M-CF=M;SHRD; Shift bits of a 64-bit destination register or memory operand to the right the number of bits specified in the CL register, while shifting in bits from the second operand.
C4-RXB.02-0.src2.0.11-F7;reg32, reg/mem32, reg32;/r;NONE;SHRX; Shift Right Logical Extended
C4-RXB.02-1.src2.0.11-F7;reg64, reg/mem64, reg64;/r;NONE;SHRX; Shift Right Logical Extended
8F-RXB.09-0.1111.0.00-12;reg32;/1;NONE;SLWPCB; Store Lightweight Profiling Control Block Address ModRM.reg augments the opcode and is assigned the value 001b. ModRM.r/m (augmented by XOP.R) specifies the register in which to put the LWPCB address. ModRM.mod must be 11b.
8F-RXB.09-1.1111.0.00-12;reg64;/1;NONE;SLWPCB; Store Lightweight Profiling Control Block Address ModRM.reg augments the opcode and is assigned the value 001b. ModRM.r/m (augmented by XOP.R) specifies the register in which to put the LWPCB address. ModRM.mod must be 11b.
F9;NONE;NONE;CF=1;STC; Set the carry flag (CF) to one.
FD;NONE;NONE;DF=1;STD; Set the direction flag (DF) to one.
AA;mem8,AL;NONE;NONE;STOS; Store the contents of the AL register to ES:rDI, and then increment or decrement rDI.
AB;mem16,AX;NONE;NONE;STOS; Store the contents of the AX register to ES:rDI, and then increment or decrement rDI.
AB;mem32,EAX;NONE;NONE;STOS; Store the contents of the EAX register to ES:rDI, and then increment or decrement rDI.
AB;mem64,RAX;NONE;NONE;STOS; Store the contents of the RAX register to ES:rDI, and then increment or decrement rDI.
AA;mem8,AL;NONE;NONE;STOSB; Store the contents of the AL register to ES:rDI, and then increment or decrement rDI.
AB;mem16,AX;NONE;NONE;STOSW; Store the contents of the AX register to ES:rDI, and then increment or decrement rDI.
AB;mem32,EAX;NONE;NONE;STOSD; Store the contents of the EAX register to ES:rDI, and then increment or decrement rDI.
AB;mem64,RAX;NONE;NONE;STOSQ; Store the contents of the RAX register to ES:rDI, and then increment or decrement rDI.
2C;AL, imm8;ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 8-bit value from the AL register and store the result in AL.
2D;AX, imm16;iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 16-bit value from the AX register and store the result in AX.
2D;EAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 32-bit value from the EAX register and store the result in EAX.
2D;RAX, imm32;id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract a sign-extended immediate 32-bit value from the RAX register and store the result in RAX.
80;reg/mem8, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 8-bit value from an 8-bit destination register or memory location.
81;reg/mem16, imm16;/5-iw;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 16-bit value from a 16-bit destination register or memory location.
81;reg/mem32, imm32;/5-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract an immediate 32-bit value from a 32-bit destination register or memory location.
81;reg/mem64, imm32;/5-id;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract a sign-extended immediate 32-bit value from a 64-bit destination register or memory location.
83;reg/mem16, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract a sign-extended immediate 8-bit value from a 16-bit register or memory location.
83;reg/mem32, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract a sign-extended immediate 8-bit value from a 32-bit register or memory location.
83;reg/mem64, imm8;/5-ib;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract a sign-extended immediate 8-bit value from a 64-bit register or memory location.
28;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of an 8-bit register from an 8-bit destination register or memory location.
29;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 16-bit register from a 16-bit destination register or memory location.
29;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 32-bit register from a 32-bit destination register or memory location.
29;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 64-bit register from a 64-bit destination register or memory location.
2A;reg8, reg/mem8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of an 8-bit register or memory operand from an 8-bit destination register.
2B;reg16, reg/mem16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 16-bit register or memory operand from a 16-bit destination register.
2B;reg32, reg/mem32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 32-bit register or memory operand from a 32-bit destination register.
2B;reg64, reg/mem64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;SUB; Subtract the contents of a 64-bit register or memory operand from a 64-bit destination register.
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/7;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;T1MSKC; Inverse Mask From Trailing Ones
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/7;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;T1MSKC; Inverse Mask From Trailing Ones
A8;AL, imm8;ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 8-bit value with the contents of the AL register and set rFLAGS to reflect the result.
A9;AX, imm16;iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 16-bit value with the contents of the AX register and set rFLAGS to reflect the result.
A9;EAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 32-bit value with the contents of the EAX register and set rFLAGS to reflect the result.
A9;RAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and a sign-extended immediate 32-bit value with the contents of the RAX register and set rFLAGS to reflect the result.
F6;reg/mem8, imm8;/0-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 8-bit value with the contents of an 8-bit register or memory operand and set rFLAGS to reflect the result.
F7;reg/mem16, imm16;/0-iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 16-bit value with the contents of a 16-bit register or memory operand and set rFLAGS to reflect the result.
F7;reg/mem32, imm32;/0-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and an immediate 32-bit value with the contents of a 32-bit register or memory operand and set rFLAGS to reflect the result.
F7;reg/mem64, imm32;/0-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and a sign-extended immediate32-bit value with the contents of a 64-bit register or memory operand and set rFLAGS to reflect the result.
84;reg/mem8, reg8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and the contents of an 8-bit register with the contents of an 8-bit register or memory operand and set rFLAGS to reflect the result.
85;reg/mem16, reg16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and the contents of a 16-bit register with the contents of a 16-bit register or memory operand and set rFLAGS to reflect the result.
85;reg/mem32, reg32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and the contents of a 32-bit register with the contents of a 32-bit register or memory operand and set rFLAGS to reflect the result.
85;reg/mem64, reg64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;TEST; and the contents of a 64-bit register with the contents of a 64-bit register or memory operand and set rFLAGS to reflect the result.
F3-0F-BC;reg16, reg/mem16;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;TZCNT; Count the number of trailing zeros in reg/mem16.
F3-0F-BC;reg32, reg/mem32;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;TZCNT; Count the number of trailing zeros in reg/mem32.
F3-0F-BC;reg64, reg/mem64;/r;OF=U-SF=U-ZF=M-AF=U-PF=U-CF=M;TZCNT; Count the number of trailing zeros in reg/mem64.
8F-RXB.09-0.dest.0.00-01;reg32, reg/mem32;/4;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;TZMSK; Mask From Trailing Zeros
8F-RXB.09-1.dest.0.00-01;reg64, reg/mem64;/4;OF=0-SF=M-ZF=M-AF=U-PF=U-CF=M;TZMSK; Mask From Trailing Zeros
0F-FF;NONE;NONE;NONE;UD0; Raise an invalid opcode exception
0F-B9;NONE;/r;NONE;UD1; Raise an invalid opcode exception
0F-0B;NONE;NONE;NONE;UD2; Raise an invalid opcode exception.
F3-0F-AE;reg32;/2;NONE;WRFSBASE; Copy the contents of the specified 32-bit general- purpose register to the lower 32 bits of FS.base.
F3-0F-AE;reg64;/2;NONE;WRFSBASE; Copy the contents of the specified 64-bit general- purpose register to FS.base.
F3-0F-AE;reg32;/3;NONE;WRGSBASE; Copy the contents of the specified 32-bit general- purpose register to the lower 32 bits of GS.base.
F3-0F-AE;reg64;/3;NONE;WRGSBASE; Copy the contents of the specified 64-bit general- purpose register to GS.base.
0F-C0;reg/mem8, reg8;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;XADD; Exchange the contents of an 8-bit register with the contents of an 8-bit destination register or memory operand and load their sum into the destination.
0F-C1;reg/mem16, reg16;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;XADD; Exchange the contents of a 16-bit register with the contents of a 16-bit destination register or memory operand and load their sum into the destination.
0F-C1;reg/mem32, reg32;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;XADD; Exchange the contents of a 32-bit register with the contents of a 32-bit destination register or memory operand and load their sum into the destination.
0F-C1;reg/mem64, reg64;/r;OF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;XADD; Exchange the contents of a 64-bit register with the contents of a 64-bit destination register or memory operand and load their sum into the destination.
90;AX, reg16;+rw;NONE;XCHG; Exchange the contents of the AX register with the contents of a 16-bit register.
90;reg16, AX;+rw;NONE;XCHG; Exchange the contents of a 16-bit register with the contents of the AX register.
90;EAX, reg32;+rd;NONE;XCHG; Exchange the contents of the EAX register with the contents of a 32-bit register.
90;reg32, EAX;+rd;NONE;XCHG; Exchange the contents of a 32-bit register with the contents of the EAX register.
90;RAX, reg64;+rq;NONE;XCHG; Exchange the contents of the RAX register with the contents of a 64-bit register.
90;reg64, RAX;+rq;NONE;XCHG; Exchange the contents of a 64-bit register with the contents of the RAX register.
86;reg/mem8, reg8;/r;NONE;XCHG; Exchange the contents of an 8-bit register with the contents of an 8-bit register or memory operand.
86;reg8, reg/mem8;/r;NONE;XCHG; Exchange the contents of an 8-bit register or memory operand with the contents of an 8-bit register.
87;reg/mem16, reg16;/r;NONE;XCHG; Exchange the contents of a 16-bit register with the contents of a 16-bit register or memory operand.
87;reg16, reg/mem16;/r;NONE;XCHG; Exchange the contents of a 16-bit register or memory operand with the contents of a 16-bit register.
87;reg/mem32, reg32;/r;NONE;XCHG; Exchange the contents of a 32-bit register with the contents of a 32-bit register or memory operand.
87;reg32, reg/mem32;/r;NONE;XCHG; Exchange the contents of a 32-bit register or memory operand with the contents of a 32-bit register.
87;reg/mem64, reg64;/r;NONE;XCHG; Exchange the contents of a 64-bit register with the contents of a 64-bit register or memory operand.
87;reg64, reg/mem64;/r;NONE;XCHG; Exchange the contents of a 64-bit register or memory operand with the contents of a 64-bit register.
D7;AL, DS;NONE;NONE;XLAT; Set AL to the contents of DS:[rBX + unsigned AL].
D7;AL, DS;NONE;NONE;XLATB; Set AL to the contents of DS:[rBX + unsigned AL].
34;AL, imm8;ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of AL with an immediate 8-bit operand and store the result in AL.
35;AX, imm16;iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of AX with an immediate 16-bit operand and store the result in AX.
35;EAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of EAX with an immediate 32-bit operand and store the result in EAX.
35;RAX, imm32;id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of RAX with a sign-extended immediate 32-bit operand and store the result in RAX.
80;reg/mem8, imm8;/6-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of an 8-bit destination register or memory operand with an 8-bit immediate value and store the result in the destination.
81;reg/mem16, imm16;/6-iw;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 16-bit destination register or memory operand with a 16-bit immediate value and store the result in the destination.
81;reg/mem32, imm32;/6-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 32-bit destination register or memory operand with a 32-bit immediate value and store the result in the destination.
81;reg/mem64, imm32;/6-id;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 64-bit destination register or memory operand with a sign-extended 32-bit immediate value and store the result in the destination.
83;reg/mem16, imm8;/6-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 16-bit destination register or memory operand with a sign-extended 8-bit immediate value and store the result in the destination.
83;reg/mem32, imm8;/6-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 32-bit destination register or memory operand with a sign-extended 8-bit immediate value and store the result in the destination.
83;reg/mem64, imm8;/6-ib;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 64-bit destination register or memory operand with a sign-extended 8-bit immediate value and store the result in the destination.
30;reg/mem8, reg8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of an 8-bit destination register or memory operand with the contents of an 8-bit register and store the result in the destination.
31;reg/mem16, reg16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 16-bit destination register or memory operand with the contents of a 16-bit register and store the result in the destination.
31;reg/mem32, reg32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 32-bit destination register or memory operand with the contents of a 32-bit register and store the result in the destination.
31;reg/mem64, reg64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 64-bit destination register or memory operand with the contents of a 64-bit register and store the result in the destination.
32;reg8, reg/mem8;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of an 8-bit destination register with the contents of an 8-bit register or memory operand and store the results in the destination.
33;reg16, reg/mem16;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 16-bit destination register with the contents of a 16-bit register or memory operand and store the results in the destination.
33;reg32, reg/mem32;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 32-bit destination register with the contents of a 32-bit register or memory operand and store the results in the destination.
33;reg64, reg/mem64;/r;OF=0-SF=M-ZF=M-AF=U-PF=M-CF=0;XOR; xor the contents of a 64-bit destination register with the contents of a 64-bit register or memory operand and store the results in the destination.
63;reg/mem16, reg16;/r;ZF=M;ARPL; Adjust the RPL of a destination segment selector to a level not less than the RPL of the segment selector specified in the 16-bit source register. (Invalid in 64-bit mode.)
0F-01-CA;NONE;NONE;AC=0;CLAC; Clear AC Flag
0F-01-DD;NONE;NONE;NONE;CLGI; Clears the global interrupt flag (GIF).
FA;NONE;NONE;VIF=M-IF=M;CLI; Clear the interrupt flag (IF) to zero.
0F-06;NONE;NONE;NONE;CLTS; Clear the task-switched (TS) flag in CR0 to 0.
F4;NONE;NONE;NONE;HLT; Halt instruction execution.
CC;NONE;NONE;AC=M-VM=0-RF=0-NT=M-IF=M-TF=0;INT_3; Trap to debugger at Interrupt 3.If a task switch occurs, all flags are modified; otherwise, setting are as follows:
0F-08;NONE;NONE;NONE;INVD; Invalidate internal caches and trigger external cache invalidations.
0F-01;mem8;/7;NONE;INVLPG; Invalidate the TLB entry for the page containing a specified
0F-01-DF;rAX, ECX;NONE;NONE;INVLPGA; Invalidates the TLB mapping for the virtual page specified in rAX and the ASID specified in ECX.
0F-01-FE;NONE;NONE;NONE;INVLPGB; Invalidates TLB entry(s) with Broadcast.
66-0F-38-82;reg32, mem128;/r;NONE;INVPCID; Invalidates the TLB entry(s) by PCID in r32 and descriptor in mem28
66-0F-38-82;reg64, mem128;/r;NONE;INVPCID; Invalidates the TLB entry(s) by PCID in r64 and descriptor in mem28
CF;NONE;NONE;ID=M-VIP=M-VIF=M-AC=M-VM=M-RF=M-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;IRET; Return from interrupt (16-bit operand size).
CF;NONE;NONE;ID=M-VIP=M-VIF=M-AC=M-VM=M-RF=M-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;IRETD; Return from interrupt (32-bit operand size).
CF;NONE;NONE;ID=M-VIP=M-VIF=M-AC=M-VM=M-RF=M-NT=M-IOPL=M-OF=M-DF=M-IF=M-TF=M-SF=M-ZF=M-AF=M-PF=M-CF=M;IRETQ; Return from interrupt (64-bit operand size).
0F-02;reg16, reg/mem16;/r;ZF=M;LAR; Reads the GDT/LDT descriptor <
« Última modificación: 1 Agosto 2020, 00:52 por FFernandez » En línea

MCKSys Argentina
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Diviértete crackeando, que para eso estamos!


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Re: Estructuras Binarias x86-64
« Respuesta #4 en: 24 Julio 2020, 02:26 »

Está construyendo un testamento...

No sería mejor colocar todo en un repo como GitHub y poner el link?

Más que nada por claridad...

Saludos!
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MCKSys Argentina

"Si piensas que algo está bien sólo porque todo el mundo lo cree, no estás pensando."

FFernandez

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Re: Estructuras Binarias x86-64
« Respuesta #5 en: 1 Agosto 2020, 19:40 »

Está construyendo un testamento...

No sería mejor colocar todo en un repo como GitHub y poner el link?

Más que nada por claridad...

Saludos!


Tengo casi listo el Testamento de Intel, lo cruzare con el de AMD y publicare solo una base de datos de instruciones conocidas.   si se puede la publico aqui.     Mas adelante publicare funciones que utilizaremos y mas Testamento...........jeje     soy todo oido, gracias
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apuromafo CLS


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Re: Estructuras Binarias x86-64
« Respuesta #6 en: 7 Agosto 2020, 21:10 »

yo sugeriría que abordaras un documento en github o gitlab, o bitbucket o cosas asi, con el tiempo evitas tener que...juntar tantos libros, además las arquitecturas mueven en cantidad de bits, tienes asm de 8, 16, 32, 64...
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