Modifico la duda que tenia antes por esto:
Buenas, tengo una duda sobre codigo VHDL con modelsim, tengo lo siguiente:


library ieee;
use ieee.std_logic_1164.all;

entity practica_1 is
  port(enable: in std_logic;
        x,y: in std_logic_vector(1 downto 0);
   z: out std_logic);
end practica_1;

architecture estructural_deco of practica_1 is
signal z1: std_logic_vector(2 downto 0);
signal zaux: std_logic;
signal y1: std_logic_vector(7 downto 0);
begin
   zaux <= ((not x(1)) and (not x(0)) and y(0))
   or
   ((not x(1)) and y(1))
   or
   ((not x(0)) and y(1) and y(0)
   );
   process(enable, z1)
   begin
      if zaux = '1' then
         z1 <= "111";
      else
         z1 <= "000";
      end if;
      if enable = '0' then
         y1 <= (others => '0');
      else
         case z1 is
           when "000" => y1 <= "00000001";
                  when "001" => y1 <= "00000010";
                  when "010" => y1 <= "00000100";
           when "011" => y1 <= "00001000";
           when "100" => y1 <= "00010000";
           when "101" => y1 <= "00100000";
           when "110" => y1 <= "01000000";        
                  when others => y1 <= "10000000";
         end case;
         z <= (y1(1) or y1(2) or y1(3) or y1(4) or y1(5) or y1(6) or y1(7));
      end if;
   end process;
end estructural_deco;

y esto es de un archivo "prefabricado" para poder realizar simulaciones con el programa:

library ieee;  
use ieee.std_logic_1164.all;

entity test_multiple is
end test_multiple;

architecture test of test_multiple is
    signal x: std_logic_vector(1 downto 0):="00";
    signal y: std_logic_vector(1 downto 0):="00";
    signal z1,z2,z3,z4,z5: std_logic;
begin
  
--  sdp: entity work.practica_1(concurrente_sdp) port map (x, y, z1);
--  pds: entity work.practica_1(concurrente_pds) port map (x, y, z2);
--  estructural_nor: entity work.practica_1(estructural_nor) port map (x, y, z3);
  e_deco: entity work.practica_1(estructural_deco) port map (x, y, z4);
--  e_mux: entity work.practica_1(estructural_mux) port map (x, y, z5);
 
  y(0) <= not y(0)after 2 ns;
  y(1) <= not y(1)after 4 ns;
  x(0) <= not x(0)after 8 ns;
  x(1) <= not x(1)after 16 ns;
  
end test;  

supestamente mi archivo complila bien, pero a la hora de compliar el otro archivo "prefabricado" para poder realizar luego la simulacion me dan los siguientes errores:

** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(13): Signal "x" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(13): Signal "z1" is type ieee.std_logic_1164.STD_LOGIC; expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(14): Signal "x" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(14): Signal "z2" is type ieee.std_logic_1164.STD_LOGIC; expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(15): Signal "x" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(15): Signal "z3" is type ieee.std_logic_1164.STD_LOGIC; expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(16): Signal "x" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(16): Signal "z4" is type ieee.std_logic_1164.STD_LOGIC; expecting type ieee.std_logic_1164.STD_LOGIC_VECTOR.
** Error: C:/Modeltech_pe_edu_10.4a/examples/test_multiple_practica1.vhd(24): VHDL Compiler exiting


Alguna idea de que puede estar mal? soy novato en esto
Gracias