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Verán, llevó tiempo trabajando en una ALU en VHDL, y he estado probando cada función por separado pero al momento de ponerlo todo en un case la simulacion ya no sirve
Quería saber si me pueden ayudar?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity prueba is
Port ( A : in STD_LOGIC_VECTOR (8 downto 1);
Rs : in STD_LOGIC_VECTOR (8 downto 1);
op: in std_logic_vector(4 downto 0);
Ci : in STD_LOGIC;
Ni : in STD_LOGIC;
Vi : in STD_LOGIC;
Zi : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (8 downto 1);
Co : out STD_LOGIC;
No : out STD_LOGIC;
Vo : out STD_LOGIC;
Zo : out STD_LOGIC);
end prueba;
architecture Behavioral of prueba is
signal s1:std_logic_vector(9 downto 1);
signal op1:std_logic_vector(4 downto 0);
begin
op1(4)<=op(4);
op1(3)<=op(3);
op1(2)<=op(2);
op1(1)<=op(1);
op1(0)<=op(0);
process(A,Rs,op1,Ci,Ni,Vi,Zi)
begin
case (op1) is
when"00001"=> --SUMA
s1<=('0'& A)+Rs+Ci;
S<=s1(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00010"=> --RESTA
s1<=('0'& A)-Rs-Ci;
S<=s1(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00011"=> --NEGACION
s1<='0'& not (A);
S<=s1(8 downto 1);
Co<='0';
No<=s1(8);
Vo<=Vi;
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00100"=> --COM A 2
s1<='0' & not (A) + 1;
S<=s1(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00101"=> --INC
s1<='0'&A+1;
S<=s1(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00110"=> --DEC
s1<='0'&A-1;
S<=s1(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"00111"=> --CLR
S<="00000000";
Co<=Ci;
No<='0';
Vo<='0';
Zo<='1';
when"01000"=> --CPC
s1<=('0'&A)-Rs-Ci;
S<=A(8 downto 1);
Co<=s1(9);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01001"=> --AND
s1<='0'&(A and Rs);
S<=s1(8 downto 1);
Co<=Ci;
No<=s1(8);
Vo<=Vi;
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01010"=>--OR
s1<='0'&(A or Rs);
S<=s1(8 downto 1);
Co<='0';
No<=s1(8);
Vo<=Vi;
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01011"=>--XOR
s1<='0'&(A xor Rs);
S<=s1(8 downto 1);
Co<='0';
No<=s1(8);
Vo<=Vi;
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01100"=>--ROL
s1(1)<=Ci;
s1(2)<=A(1);
s1(3)<=A(2);
s1(4)<=A(3);
s1(5)<=A(4);
s1(6)<=A(5);
s1(7)<=A(6);
s1(8)<=A(7);
S<=s1(8 downto 1);
Co<=A(8);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01101"=>--ROR
s1(1)<=A(2);
s1(2)<=A(3);
s1(3)<=A(4);
s1(4)<=A(5);
s1(5)<=A(6);
s1(6)<=A(7);
s1(7)<=A(8);
s1(8)<=Ci;
S<=s1(8 downto 1);
Co<=A(1);
No<=s1(8);
Vo<=s1(9) xor s1(8);
Zo<=not(s1(9)or s1(8)or s1(7)or s1(6)or s1(5)or s1(4)or s1(3)or s1(2)or s1(1));
when"01110"=>--CI-IN
Co<='1';
No<=Ni;
Vo<=Vi;
Zo<=Zi;
S<="00000000";
when"01111"=>
Co<='0';
No<=Ni;
Vo<=Vi;
Zo<=Zi;
S<="00000000";
when"10000"=>
Co<=Ci;
No<='1';
Vo<=Vi;
Zo<=Zi;
S<="00000000";
when"10001"=>
Co<=Ci;
No<='0';
Vo<=Vi;
Zo<=Zi;
S<="00000000";
when"10010"=>
Co<=Ci;
No<=Ni;
Vo<='1';
Zo<=Zi;
S<="00000000";
when"10011"=>
Co<=Ci;
No<=Ni;
Vo<='0';
Zo<=Zi;
S<="00000000";
when"10100"=>
Co<=Ci;
No<=Ni;
Vo<=Vi;
Zo<='1';
S<="00000000";
when"10101"=>
Co<=Ci;
No<=Ni;
Vo<=Vi;
Zo<='0';
S<="00000000";
when others=>
Co <= Ci;-- otros
No <= Ni;
Vo <= Vi;
Zo <= Zi;
S <= "00000000";
end case;
end process;
end Behavioral;
Este es mi codigo, si pudieran ayudarme estaría o corregirme en algo
Saludos!