Foro de elhacker.net

LIBRARY ieee; 

 USE ieee.STD_LOGIC_1164.ALL; 


 ENTITY BiestableD IS 

 PORT ( D, CLK : IN std_logic; 

 rstH : IN std_logic; 

 Q : OUT std_logic); 

 END BiestableD ; 

ARCHITECTURE BiestableDarq OF BiestableD IS 

 BEGIN 

 PROCESS (CLK, rstH) 

 BEGIN 

 IF (rstH = ‘1’) THEN 

 Q <= ‘0’; 

 ELSIF (CLK’event and CLK = ‘1’) THEN 

 Q <= D; 

 END IF; 

 END PROCESS; 

 END BiestableDarq;